High performance low overhead template-based Cell-Interleave Pipeline (TCIP) for asynchronous-logic QDI circuits.
Weng-Geng HoNan LiuKyaw Zwa Lwin NeKwen-Siong ChongBah-Hwee GweeJoseph Sylvester ChangPublished in: ISCAS (2016)
Keyphrases
- low overhead
- delay insensitive
- asynchronous circuits
- high reliability
- shift register
- logic synthesis
- load balancing
- built in self test
- shared memory
- energy efficient
- high level synthesis
- digital circuits
- parallel architecture
- low cost
- high precision
- communication cost
- logic circuits
- high speed
- wireless sensor networks
- intelligent agents
- context aware
- peer to peer
- chip design
- multi agent