A low power 16-bit Booth Leapfrog array multiplier using Dynamic Adders.
Kwen-Siong ChongBah-Hwee GweeJoseph Sylvester ChangPublished in: ISCAS (2) (2004)
Keyphrases
- low power
- high speed
- low cost
- power consumption
- image sensor
- logic circuits
- bit parallel
- power dissipation
- vlsi architecture
- programmable logic
- single chip
- low power consumption
- wireless transmission
- digital signal processing
- high power
- vlsi circuits
- cmos technology
- pattern matching
- analog to digital converter
- power reduction
- mixed signal
- random access memory