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Area-efficient and low stand-by power 1k-byte transmission-gate-based non-imprinting high-speed erase (TNIHE) SRAM.
Weng-Geng Ho
Kyaw Zwa Lwin Ne
N. Prashanth Srinivas
Kwen-Siong Chong
Tony Tae-Hyoung Kim
Bah-Hwee Gwee
Published in:
ISCAS (2016)
Keyphrases
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high speed
power consumption
low power
data transmission
neural network
cmos technology
error correcting codes