Tom Chen

Publication Activity (10 Years)

Years Active: 1991-2017
Publications (10 Years): 8

Top Topics

Design Automation

Cmos Technology

Delay Insensitive

Top Venues

Publications

Lang Yang, Tom Chen
A handheld electrochemical sensing platform for point-of-care diagnostic applications. BioCAS (2017)
Yishai Statter, Tom Chen
A novel high-throughput method for table look-up based analog design automation. Integr. 52 (2016)
Lang Yang, Tom Chen
A compact signal generation and acquisition circuit for electrochemical impedance spectroscopy. BioCAS (2016)
William Tedjo, Rachel Feeny, Chad Eitel, Luke Schwerdtfeger, Stacy Willett, Charles Henry, Stuart Tobet, Tom Chen
Design of an integrated microelectrode array system for high spatiotemporal resolution chemical imaging. BioCAS (2016)
Mozammel Hossain, John Badar, Jack DiLullo, Tom Chen
A practical automated timing and physical design implementation methodology for the synchronous asynchronous interface and multi-voltage domain in high-speed synthesis. Microprocess. Microsystems 45 (2016)
Abhiram Reddy Gundla, Tom Chen
A 0.2 nJ/bit QPSK transmitter with tuning for process variation for biomedical telemetry in the MedRadio band of 401-457 MHz. MWSCAS (2016)
Abhiram Reddy Gundla, Tom Chen
An efficient multi channel, 425µW QPSK transmitter with tuning for process variation in the Medical Implantable Communications Service (MICS) band of 402-405MHz. VLSI-SoC (2016)
Yishai Statter, Tom Chen
Γ (Gamma): A SaaS-enabled fast and accurate analog design System. Integr. 55 (2016)
Mozammel Hossain, Chirag Desai, Tom Chen, Vikas Agarwal
Synthesis-based design and implementation methodology of high-speed, high-performing unit: L2 cache unit design. Integr. 49 (2015)
Abhiram Reddy Gundla, Tom Chen
A low power frequency synthesizer for biosensor applications in the MedRadio band. MWSCAS (2015)
William Wilson, Tom Chen
Design of a 50MΩ Transimpedance Amplifier with 0.98fa/vHz Input Inferred Noise in a 0.18µM CMOS Technology. BIODEVICES (2014)
Hai Chi, Tom Chen
A CMOS Temperature Sensor with -0.34°C to 0.27°C Inaccuracy from -30°C to 80°C. ISVLSI (2014)
Ryan Selby, Kern Tucker, William Wilson, Tom Chen
A 0.18µm CMOS switched-capacitor amplifier using current-starving inverter based op-amp for low-power biosensor applications. LASCAS (2013)
Ryan Selby, Tom Chen
A 0.18µm CMOS 2nd Order Sigma-Delta Modulator for Low-power Biosensor Applications. BIODEVICES (2013)
Ryan Selby, Tom Chen
A 2nd Order CMOS Sigma-Delta Modulator Design Suitable for Low-Power Biosensor Applications. BIOSTEC (Selected Papers) (2013)
Kristin Scholfield, Tom Chen
A Low Power 15-Bit Decimator in 0.18um CMOS for Biomedical Applications. DSD (2013)
William Wilson, Tom Chen, Ryan Selby
A current-starved inverter-based differential amplifier design for ultra-low power applications. LASCAS (2013)
Charles Thangaraj, Alkan Cengiz, Tom Chen
Rapid design space exploration using legacy design data and technology scaling trend. Integr. 43 (2) (2010)
Zach Cashero, Allen Chen, Ryan Hoppal, Tom Chen
Fast Evaluation of Analog Circuits Using Linear Programming. ISVLSI (2010)
Chandrika Jena, Tim Mason, Tom Chen
On power and performance tradeoff of L2 cache compression. APCCAS (2010)
Allen Chen, Ryan Hoppal, Tom Chen
On CMOS Memory Design in Low Supply Voltage for Integrated Biosensor Applications. DSD (2010)
Charles Thangaraj, Robert Pownall, Phil Nikkel, Guangwei Yuan, Kevin L. Lear, Tom Chen
Fully CMOS-Compatible On-Chip Optical Clock Distribution and Recovery. IEEE Trans. Very Large Scale Integr. Syst. 18 (10) (2010)
Charles Thangaraj, Tom Chen
Design target exploration for meeting time-to-market using pareto analysis. ISCAS (2008)
Charles Thangaraj, Tom Chen
Early Design Phase Power Performance Trade-Offs Using In-Situ Macro Models. DELTA (2008)
Daniela De Venuto, Tom Chen
Editorial. Microelectron. J. 38 (4-5) (2007)
Charles Thangaraj, Tom Chen
Power andPerformance Analysis for Early Design Space Exploration. ISVLSI (2007)
Jayashree Sridharan, Tom Chen
Modeling multiple input switching of CMOS gates in DSM technology using HDMR. DATE (2006)
Jayashree Sridharan, Tom Chen
Gate Delay Modeling with Multiple Input Switching for Static (Statistical) Timing Analysis. VLSI Design (2006)
Ajith Chandy, Tom Chen
Performance Driven Decoupling Capacitor Allocation Considering Data and Clock Interactions. DATE (2005)
Daniela De Venuto, Tom Chen
International Symposium on Quality Electronic Design. Microelectron. J. 36 (9) (2005)
Vinil Varghese, Tom Chen, Peter Young
Stability analysis of active clock deskewing systems using a control theoretic approach. ASP-DAC (2005)
Medha Kulkarni, Tom Chen
A sensitivity-based approach to analyzing signal delay uncertainty of coupled interconnects. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 24 (9) (2005)
Vinil Varghese, Tom Chen, Peter Michael Young
Systematic Analysis of Active Clock Deskewing Systems Using Control Theory. DATE (2005)
Vinil Varghese, Tom Chen, Peter Young
Stability analysis of active clock deskewing systems using a control theoretic approach. ACC (2005)
Geun Rae Cho, Tom Chen
Synthesis of single/dual-rail mixed PTL/static logic for low-power applications. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 23 (2) (2004)
Anneliese Amschler Andrews, Andrew O'Fallon, Tom Chen
RUBASTEM: A Method for Testing VHDL Behavioral Models. HASE (2004)
Tom Chen, Amjad Hajjar
Statistical timing analysis of coupled interconnects using quadratic delay-change characteristics. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 23 (12) (2004)
Gerald Esch Jr., Tom Chen
Near-linear CMOS I/O driver with less sensitivity to process, voltage, and temperature variations. IEEE Trans. Very Large Scale Integr. Syst. 12 (11) (2004)
Gerald Esch Jr., Tom Chen
Design of CMOS IO Drivers with Less Sensitivity to Process, Voltage, and Temperature Variations. DELTA (2004)
Medha Kulkarni, Tom Chen
A Sensitivity Based Approach to Analyzing Signal Delay Uncertainty of Coupled Interconnects. ISQED (2004)
Geun Rae Cho, Tom Chen
On Single/Dual-Rail Mixed PTL/Static Circuits in Floating-Body SOI and Bulk CMOS: A Comparative Assessment. VLSI Design (2003)
Geun Rae Cho, Tom Chen
Comparative Assessment of Adaptive Body-Bias SOI Pass-Transistor Logic. ISQED (2003)
Jinsang Kim, Tom Chen
A VLSI architecture for video-object segmentation. IEEE Trans. Circuits Syst. Video Technol. 13 (1) (2003)
Anneliese Amschler Andrews, Andrew O'Fallon, Tom Chen
A Rule-Based Software Testing Method for VHDL Models. VLSI-SOC (2003)
Chetan Despande, Tom Chen
Design of a CMOS test chip for package models and I/O characteristics verification. ASP-DAC (2003)
Tom Chen, Amjad Hajjar
Analyzing Statistical Timing Behavior of Coupled Interconnects Using Quadratic Delay Change Characteristics. ISQED (2003)
Geun Rae Cho, Tom Chen
Applications of Evolution Algorithms to the synthesis of single/Dual-rail mixed PTL/Static Logic for low-Power Applications. SEAL (2002)
Amjad Hajjar, Tom Chen
Improving the Efficiency and Quality of Simulation-Based Behavioral Model Verification Using Dynamic Bayesian Criteria. ISQED (2002)
Geun Rae Cho, Tom Chen
Mixed PTL/Static Logic Synthesis Using Genetic Algorithms for Low-Power Applications. ISQED (2002)
Amjad Hajjar, Tom Chen
An Accurate Coverage Forecasting Model for Behavioral Model Verification. DELTA (2002)
Geun Rae Cho, Tom Chen
On The Impact of Technology Scaling On Mixed PTL/Static Circuits. ICCD (2002)
Geun Rae Cho, Tom Chen
On the Impact of Fanout Optimization and Redundant Buffer Removal for Mixed PTL Synthesis. IWLS (2002)
Tom Chen, Andre Bai, Amjad Hajjar, Anneliese Amschler Andrews, Charles Anderson
Fast Anti-Random (FAR) Test Generation to Improve the Quality of Behavioral Model Verification. J. Electron. Test. 18 (6) (2002)
Amjad Hajjar, Tom Chen, Isabelle Munn, Anneliese Amschler Andrews, Maria Bjorkman
High quality behavioral verification using statistical stopping criteria. DATE (2001)
Jinsang Kim, Tom Chen
Multiple feature clustering for image sequence segmentation. Pattern Recognit. Lett. 22 (11) (2001)
Tom Chen
Impact of On-Chip Inductance When Transitioning from Al to Cu Based Technology. ISQED (2001)
Jinsang Kim, Tom Chen
Real-time Video Objects Segmentation using a Highly Pipelined Microarchitecture. VIIP (2001)
Amjad Hajjar, Tom Chen, Isabelle Munn, Anneliese Amschler Andrews, Maria Bjorkman
Stopping Criteria Comparison: Towards High Quality Behavioral Verification. ISQED (2001)
Geun Rae Cho, Tom Chen
On Mixed PTL/Static Logic for Low-power and High-speed Circuits. VLSI Design 2001 (3) (2001)
Tom Chen
On the impact of on-chip inductance on signal nets under the influence of power grid noise. DATE (2001)
Amjad Hajjar, Tom Chen, Anneliese von Mayrhauser
On statistical behavior of branch coverage in testing behavioral VHDL models. HLDVT (2000)
Tom Chen, Anneliese von Mayrhauser, Amjad Hajjar, Charles Anderson, Mehmet Sahinoglu
Achieving the Quality of Verification for Behavioral Models with Minimum Effort. ISQED (2000)
Jinsang Kim, Tom Chen
A VLSI Architecture for Image Sequence Segmentation using Edge Fusion. CAMP (2000)
Jinsang Kim, Tom Chen
Segmentation of Image Sequences Using SOFM Networks. ICPR (2000)
Anneliese von Mayrhauser, Tom Chen, Jan Kok, Chuck Anderson, Anita Read, Amjad Hajjar
On choosing test criteria for behavioral level hardware design verification. HLDVT (2000)
Amjad Hajjar, Tom Chen
VLSI Architecture for Real-Time Edge Linking. IEEE Trans. Pattern Anal. Mach. Intell. 21 (1) (1999)
Tom Chen, Isabelle Munn, Anneliese von Mayrhauser, Amjad Hajjar
Efficient Verification of Behavioral Models Using Sequential Sampling Technique. VLSI (1999)
Tom Chen, Anneliese von Mayrhauser, Amjad Hajjar, Charles Anderson, Mehmet Sahinoglu
How Much Testing is Enough? Applying Stopping Rules to Behavioral Model Testing. HASE (1999)
Tom Chen, Glen Sunada, Jain Jin
COBRA: a 100-MOPS single-chip programmable and expandable FFT. IEEE Trans. Very Large Scale Integr. Syst. 7 (2) (1999)
Von-Kyoung Kim, Tom Chen, Mick Tegethoff
Fault Coverage Estimation for Early Stage of VLSI Design. Great Lakes Symposium on VLSI (1999)
Von-Kyoung Kim, Tom Chen
Assessing Defect Coverage of Memory Testing Algorithms. Great Lakes Symposium on VLSI (1999)
Von-Kyoung Kim, Tom Chen
On comparing functional fault coverage and defect coverage for memory testing. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 18 (11) (1999)
Anneliese von Mayrhauser, Andre Bai, Tom Chen, Charles Anderson, Amjad Hajjar
Fast Antirandom (FAR) Test Generation. HASE (1998)
Fahad M. Alzahrani, Tom Chen
A Real-Time Edge Detector: Algorithm and VLSI Architecture. Real Time Imaging 3 (5) (1997)
Von-Kyoung Kim, Tom Chen, Mick Tegethoff
ASIC Manufacturing Test Cost Prediction at Early Design Stage. ITC (1997)
Fahad M. Alzahrani, Tom Chen
A real-time high performance edge detector for computer vision applications. ASP-DAC (1997)
Mick Tegethoff, Tom Chen
Simulation Techniques for the Manufacturing Test of MCMs. J. Electron. Test. 10 (1-2) (1997)
Mick Tegethoff, Tom Chen
Sensitivity Analysis of Critical Parameters in Board Test. IEEE Des. Test Comput. 13 (1) (1996)
Charles Anderson, Anneliese von Mayrhauser, Tom Chen
Assessing Neural Networks as Guides for Testing Activities. IEEE METRICS (1996)
Von-Kyoung Kim, Mick Tegethoff, Tom Chen
ASIC Yield Estimation at Early Design Cycle. ITC (1996)
Xiao-Dong Wang, Tom Chen
Performance and Area Optimization of VLSI Systems Using Genetic Algorithms. VLSI Design 3 (1) (1995)
Glen Sunada, Jain Jin, Matt Berzins, Tom Chen
COBRA: An 1.2 Million Transistor Expandable Column FFT Chip. ICCD (1994)
Mick Tegethoff, Tom Chen
Manufacturing-Test Simulator: A Concurrent-Engineering Tool for Boards and MCMs. ITC (1994)
Fahad M. Alzahrani, Tom Chen
On-Chip TEC-QED ECC for Ultra-Large, Single-Chip Memory Systems. ICCD (1994)
Mick Tegethoff, Tom Chen
Defects, Fault Coverage, Yield and Cost in Board Manufacturing. ITC (1994)
Tom Chen, Glen Sunada
Design of a self-testing and self-repairing structure for highly hierarchical ultra-large capacity memory chips. IEEE Trans. Very Large Scale Integr. Syst. 1 (2) (1993)
Tom Chen, Li Zhu
An expandable column fft architecture using circuit switching networks. J. VLSI Signal Process. 6 (3) (1993)
Tom Chen, Glen Sunada
A Self-Testing and Self-Repairing Structure for Ultra-Large Capacity Memories. ITC (1992)
Tom Chen, Glen Sunada
An Ultra-Large Capacity Single-Chip Memory Architecture With Self-Testing and Self-Repairing. ICCD (1992)
Tom Chen, Li Zhu
A Fast 1024-Point FFT Architecture. ICPP (1) (1991)