Geun Rae Cho

Publication Activity (10 Years)

Years Active: 2001-2014
Publications (10 Years): 0

Top Topics

Expectation Maximization

Modeling Framework

Top Venues

IEICE Electron. Express

Publications

Moon Gi Seok, Daejin Park, Geun Rae Cho, Tag Gon Kim
Framework for simulation of the Verilog/SPICE mixed model: Interoperation of Verilog and SPICE simulators using HLA/RTI for model reusability. VLSI-SoC (2014)
Geun Rae Cho, Kyung Woon Hwang, Tag Gon Kim
A high supply voltage bandgap reference circuit using drain-extended MOS devices. IEICE Electron. Express 10 (8) (2013)
Geun Rae Cho, Tom Chen
Synthesis of single/dual-rail mixed PTL/static logic for low-power applications. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 23 (2) (2004)
Geun Rae Cho, Tom Chen
On Single/Dual-Rail Mixed PTL/Static Circuits in Floating-Body SOI and Bulk CMOS: A Comparative Assessment. VLSI Design (2003)
Geun Rae Cho, Tom Chen
Comparative Assessment of Adaptive Body-Bias SOI Pass-Transistor Logic. ISQED (2003)
Geun Rae Cho, Tom Chen
Applications of Evolution Algorithms to the synthesis of single/Dual-rail mixed PTL/Static Logic for low-Power Applications. SEAL (2002)
Geun Rae Cho, Tom Chen
Mixed PTL/Static Logic Synthesis Using Genetic Algorithms for Low-Power Applications. ISQED (2002)
Geun Rae Cho, Tom Chen
On The Impact of Technology Scaling On Mixed PTL/Static Circuits. ICCD (2002)
Geun Rae Cho, Tom Chen
On the Impact of Fanout Optimization and Redundant Buffer Removal for Mixed PTL Synthesis. IWLS (2002)
Geun Rae Cho, Tom Chen
On Mixed PTL/Static Logic for Low-power and High-speed Circuits. VLSI Design 2001 (3) (2001)