Framework for simulation of the Verilog/SPICE mixed model: Interoperation of Verilog and SPICE simulators using HLA/RTI for model reusability.
Moon Gi SeokDaejin ParkGeun Rae ChoTag Gon KimPublished in: VLSI-SoC (2014)
Keyphrases
- formal model
- mathematical model
- probabilistic model
- computational model
- theoretical framework
- unified model
- data mining
- modeling framework
- high level
- similarity measure
- data model
- statistical model
- expectation maximization
- simulation model
- theoretical foundation
- conceptual model
- data sets
- management system
- prior knowledge
- case study
- decision making
- databases