Synthesis of single/dual-rail mixed PTL/static logic for low-power applications.

Geun Rae Cho Tom Chen

Published in: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. (2004)

Keyphrases

low power
high speed
logic circuits
power consumption
low cost
delay insensitive
high power
single chip
logic synthesis
vlsi circuits
vlsi architecture
wireless transmission
digital signal processing
low power consumption
real time
mixed signal
signal processing
image sensor
cmos technology
signal processor
gate array