Narendra Devta-Prasanna

Publication Activity (10 Years)

Years Active: 2005-2012
Publications (10 Years): 0

Top Topics

Identification Rate

Evaluation Methods

Top Venues

Publications

Wei Zhao, Sreejit Chakravarty, Junxia Ma, Narendra Devta-Prasanna, Fan Yang, Mohammad Tehranipoor
A novel method for fast identification of peak current during test. VTS (2012)
Sreejit Chakravarty, Narendra Devta-Prasanna, Arun Gunda, Junxia Ma, Fan Yang, H. Guo, R. Lai, D. Li
Silicon evaluation of faster than at-speed transition delay tests. VTS (2012)
Narendra Devta-Prasanna, Arun Gunda, Sudhakar M. Reddy, Irith Pomeranz
Multiple fault activation cycle tests for transistor stuck-open faults. ITC (2010)
Narendra Devta-Prasanna, Arun Gunda
Clock Gate Test Points. ITC (2010)
Fan Yang, Sreejit Chakravarty, Narendra Devta-Prasanna, Sudhakar M. Reddy, Irith Pomeranz
Improving the Detectability of Resistive Open Faults in Scan Cells. DFT (2009)
Sandeep Kumar Goel, Narendra Devta-Prasanna, Mark Ward
Comparing the effectiveness of deterministic bridge fault and multiple-detect stuck fault patterns for physical bridge defects: A simulation and silicon study. ITC (2009)
Narendra Devta-Prasanna, Sandeep Kumar Goel, Arun Gunda, Mark Ward, P. Krishnamurthy
Accurate measurement of small delay defect coverage of test patterns. ITC (2009)
Fan Yang, Sreejit Chakravarty, Narendra Devta-Prasanna, Sudhakar M. Reddy, Irith Pomeranz
Detectability of internal bridging faults in scan chains. ASP-DAC (2009)
Sandeep Kumar Goel, Narendra Devta-Prasanna, Ritesh P. Turakhia
Effective and Efficient Test Pattern Generation for Small Delay Defect. VTS (2009)
Fan Yang, Sreejit Chakravarty, Narendra Devta-Prasanna, Sudhakar M. Reddy, Irith Pomeranz
An Enhanced Logic BIST Architecture for Online Testing. IOLTS (2008)
Fan Yang, Sreejit Chakravarty, Narendra Devta-Prasanna, Sudhakar M. Reddy, Irith Pomeranz
On the Detectability of Scan Chain Internal Faults - An Industrial Case Study. VTS (2008)
Fan Yang, Sreejit Chakravarty, Narendra Devta-Prasanna, Sudhakar M. Reddy, Irith Pomeranz
Detection of Internal Stuck-open Faults in Scan Chains. ITC (2008)
Ahmad A. Al-Yamani, Narendra Devta-Prasanna, Arun Gunda
Comparative study of centralised and distributed compatibility-based test data compression. IET Comput. Digit. Tech. 2 (2) (2008)
Fan Yang, Sreejit Chakravarty, Narendra Devta-Prasanna, Sudhakar M. Reddy, Irith Pomeranz
Detection of Transistor Stuck-Open Faults in Asynchronous Inputs of Scan Cells. DFT (2008)
Ahmad A. Al-Yamani, Narendra Devta-Prasanna, Arun Gunda
Systematic Scan Reconfiguration. ASP-DAC (2007)
Ahmad A. Al-Yamani, Narendra Devta-Prasanna, Erik Chmelar, M. Grinchuk, Arun Gunda
Scan Test Cost and Power Reduction Through Systematic Scan Reconfiguration. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26 (5) (2007)
Narendra Devta-Prasanna, Arun Gunda, P. Krishnamurthy, Sudhakar M. Reddy, Irith Pomeranz
A Unified Method to Detect Transistor Stuck-Open Faults and Transition Delay Faults. ETS (2006)
Narendra Devta-Prasanna, Arun Gunda, P. Krishnamurthy, Sudhakar M. Reddy, Irith Pomeranz
Test Generation for Open Defects in CMOS Circuits. DFT (2006)
Ahmad A. Al-Yamani, Narendra Devta-Prasanna, Arun Gunda
Should Illinois-Scan Based Architectures be Centralized or Distributed? DFT (2005)
Narendra Devta-Prasanna, Arun Gunda, P. Krishnamurthy, Sudhakar M. Reddy, Irith Pomeranz
A Novel Method of Improving Transition Delay Fault Coverage Using Multiple Scan Enable Signals. ICCD (2005)
Narendra Devta-Prasanna, Arun Gunda, P. Krishnamurthy, Sudhakar M. Reddy, Irith Pomeranz
Methods for improving transition delay fault coverage using broadside tests. ITC (2005)
Narendra Devta-Prasanna, Sudhakar M. Reddy, Arun Gunda, P. Krishnamurthy, Irith Pomeranz
Improved Delay Fault Coverage Using Subsets of Flip-flops to Launch Transitions. Asian Test Symposium (2005)