Test Generation for Open Defects in CMOS Circuits.
Narendra Devta-PrasannaArun GundaP. KrishnamurthySudhakar M. ReddyIrith PomeranzPublished in: DFT (2006)
Keyphrases
- test generation
- analog vlsi
- delay insensitive
- circuit design
- high speed
- design automation
- test cases
- vlsi circuits
- symbolic execution
- cmos technology
- test sequences
- chip design
- software testing
- power dissipation
- quality assurance
- floating gate
- random access memory
- low voltage
- static analysis
- mutation testing
- test data generation
- low power
- low cost
- asynchronous circuits
- power consumption
- artificial intelligence
- databases
- quality control
- human visual system
- code coverage
- database