Jatindra Kumar Deka

Publication Activity (10 Years)

Years Active: 1999-2023
Publications (10 Years): 34

Top Topics

Test Generation

Fault Detection

Top Venues

J. Electron. Test.

HPCC/SmartCity/DSS

Publications

Kunwer Mrityunjay Singh, Jatindra Kumar Deka, Santosh Biswas
Incomplete Testing of SOC. J. Electron. Test. 39 (3) (2023)
Nanu Alan Kachari, Santosh Biswas, Jatindra Kumar Deka
Conversion of Virtual Lab Experiments using FOSS: A Case Study of Virtual Labs by NMEICT. TALE (2021)
Sisir Kumar Jena, Santosh Biswas, Jatindra Kumar Deka
Retesting Defective Circuits to Allow Acceptable Faults for Yield Enhancement. J. Electron. Test. 37 (5) (2021)
Kunwer Mrityunjay Singh, Santosh Biswas, Jatindra Kumar Deka
ATPG for Incomplete Testing of SOC Considering Bridging Faults. TENCON (2021)
Biswajit Bhowmik, Jatindra Kumar Deka, Santosh Biswas
Selective Fault-Masking for Improving Yield and Performance of On-Chip Networks. SMC (2021)
Sisir Kumar Jena, Santosh Biswas, Jatindra Kumar Deka
Approximate Testing of Digital VLSI Circuits using Error Significance based Fault Analysis. VDAT (2020)
Biswajit Bhowmik, Santosh Biswas, Jatindra Kumar Deka
Test Methodology for Analysis of Coexistent Logic-Level Faults in NoC Channels. SMC (2020)
Mousum Handique, Jatindra Kumar Deka, Santosh Biswas
A Fault Detection Scheme for Reversible Circuits using -Ve Control k-CNOT Based Circuit. TENCON (2020)
Biswajit Bhowmik, Santosh Biswas, Jatindra Kumar Deka, Bhargab B. Bhattacharya
Locating Open-Channels in Octagon Networks on Chip-Microprocessors. ISVLSI (2020)
Biswajit Bhowmik, Jatindra Kumar Deka, Santosh Biswas
Reliability Monitoring in a Smart NoC Component. ICECS (2020)
Biswajit Bhowmik, Jatindra Kumar Deka, Santosh Biswas
Improving Reliability in Spidergon Network on Chip-Microprocessors. MWSCAS (2020)
Sisir Kumar Jena, Santosh Biswas, Jatindra Kumar Deka
Maximizing Yield through Retesting of Rejected Circuits using Approximation Technique. TENCON (2020)
Mousum Handique, Jatindra Kumar Deka, Santosh Biswas
An Efficient Test Set Construction Scheme for Multiple Missing-Gate Faults in Reversible Circuits. J. Electron. Test. 36 (1) (2020)
Biswajit Bhowmik, Santosh Biswas, Jatindra Kumar Deka, Bhargab B. Bhattacharya
A Low-Cost Test Solution for Reliable Communication in Networks-on-Chip. J. Electron. Test. 35 (2) (2019)
Sisir Kumar Jena, Santosh Biswas, Jatindra Kumar Deka
Systematic Design of Approximate Adder Using Significance Based Gate-Level Pruning (SGLP) for Image Processing Application. PReMI (2) (2019)
Mousum Handique, Santosh Biswas, Jatindra Kumar Deka
Test Generation for Bridging Faults in Reversible Circuits Using Path-Level Expressions. J. Electron. Test. 35 (4) (2019)
Biswajit Bhowmik, Jatindra Kumar Deka, Santosh Biswas, Bhargab B. Bhattacharya
Performance-Aware Test Scheduling for Diagnosing Coexistent Channel Faults in Topology-Agnostic Networks-on-Chip. ACM Trans. Design Autom. Electr. Syst. 24 (2) (2019)
Biswajit Bhowmik, Jatindra Kumar Deka, Santosh Biswas
On-Line Analysis of Stuck-at Faults in On-Chip Network Interconnects. J. Circuits Syst. Comput. 27 (13) (2018)
Biswajit Bhowmik, Santosh Biswas, Jatindra Kumar Deka, Bhargab B. Bhattacharya
Reliability-Aware Test Methodology for Detecting Short-Channel Faults in On-Chip Networks. IEEE Trans. Very Large Scale Integr. Syst. 26 (6) (2018)
Biswajit Bhowmik, Jatindra Kumar Deka, Santosh Biswas
A Time-Optimized Scheme Towards Analysis of Channel-Shorts in on-Chip Networks. J. Electron. Test. 33 (2) (2017)
Biswajit Bhowmik, Jatindra Kumar Deka, Santosh Biswas
Charka: A reliability-aware test scheme for diagnosis of channel shorts beyond mesh NoCs. DATE (2017)
Biswajit Bhowmik, Santosh Biswas, Jatindra Kumar Deka
A Reliability-Aware Topology-Agnostic Test Scheme for Detecting, and Diagnosing Interconnect Shorts in On-chip Networks. HPCC/SmartCity/DSS (2016)
Biswajit Bhowmik, Jatindra Kumar Deka, Santosh Biswas
An on-line test solution for addressing interconnect shorts in on-chip networks. IOLTS (2016)
Biswajit Bhowmik, Jatindra Kumar Deka, Santosh Biswas
When Clustering Shows Optimality towards Analyzing Stuck-at Faults in Channels of On-chip Networks. HPCC/SmartCity/DSS (2016)
Biswajit Bhowmik, Santosh Biswas, Jatindra Kumar Deka, Bhargab B. Bhattacharya
Detecting and diagnosing open faults in NoC channels on activation of diagonal nodes. SMC (2016)
Biswajit Bhowmik, Jatindra Kumar Deka, Santosh Biswas, Bhargab B. Bhattacharya
On-line detection and diagnosis of stuck-at faults in channels of NoC-based systems. SMC (2016)
Biswajit Bhowmik, Jatindra Kumar Deka, Santosh Biswas
Towards a Scalable Test Solution for the Analysis of Interconnect Shorts in On-chip Networks. MASCOTS (2016)
Biswajit Bhowmik, Santosh Biswas, Jatindra Kumar Deka, Bhargab B. Bhattacharya
One poison is antidote against another poison. SMC (2016)
Biswajit Bhowmik, Santosh Biswas, Jatindra Kumar Deka
An odd-even scheme to prevent a packet from being corrupted and dropped in fault tolerant NoCs. IOLTS (2016)
Biswajit Bhowmik, Jatindra Kumar Deka, Santosh Biswas, Bhargab B. Bhattacharya
A topology-agnostic test model for link shorts in on-chip networks. SMC (2016)
Biswajit Bhowmik, Jatindra Kumar Deka, Santosh Biswas
Directed Symbolic Execution for VLSI Circuits. SMC (2015)
Biswajit Bhowmik, Santosh Biswas, Jatindra Kumar Deka
An Optimal Diagnosis of NoC Interconnects on Activation of Diagonal Routers. SMC (2015)
Biswajit Bhowmik, Jatindra Kumar Deka, Santosh Biswas
Reliability on Top of Best Effort Delivery: Maximal Connectivity Test on NoC Interconnects. COMPUTE (2015)
Biswajit Bhowmik, Santosh Biswas, Jatindra Kumar Deka
A packet address driven test strategy for stuck-at faults in networks-on-chip interconnects. MED (2015)
Biswajit Bhowmik, Santosh Biswas, Jatindra Kumar Deka
Detection of faulty interswitch links in 2-D mesh network-on-chips. IEEE ANTS (2014)
Khan Ajoy, Kushagra Misra, Santosh Biswas, Jatindra Kumar Deka, Hemangee K. Kapoor
Fair diagnosability in PN-based DES models. ICCA (2010)
Moi Riba, Jatindra Kumar Deka
Variable Ordering of BDDs using Genetic Algorithm. IICAI (2005)
Jatindra Kumar Deka
Reasoning about Extremal Properties of Events. TIME (2003)
Pallab Dasgupta, P. P. Chakrabarti, Jatindra Kumar Deka, Sriram Sankaranarayanan
Min-max Computation Tree Logic. Artif. Intell. 127 (1) (2001)
Jatindra Kumar Deka, S. Chaki, Pallab Dasgupta, P. P. Chakrabarti
Abstractions for model checking of event timings. ISCAS (5) (2001)
Pallab Dasgupta, Jatindra Kumar Deka, Partha Pratim Chakrabarti
Model checking on timed-event structures. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 19 (5) (2000)
Jatindra Kumar Deka, Pallab Dasgupta, P. P. Chakrabarti
An Efficiently Checkable Subset of TCTL for Formal Verification of Transition Systems with Delays. VLSI Design (1999)