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An Efficiently Checkable Subset of TCTL for Formal Verification of Transition Systems with Delays.

Jatindra Kumar DekaPallab DasguptaP. P. Chakrabarti
Published in: VLSI Design (1999)
Keyphrases
  • formal verification
  • model checking
  • transition systems
  • model checker
  • temporal logic
  • concurrent systems
  • finite state
  • formal methods
  • formal specification
  • description language