Retesting Defective Circuits to Allow Acceptable Faults for Yield Enhancement.
Sisir Kumar JenaSantosh BiswasJatindra Kumar DekaPublished in: J. Electron. Test. (2021)
Keyphrases
- built in self test
- fault models
- image enhancement
- high speed
- fault detection
- tunnel diode
- fault diagnosis
- image processing
- neural network
- delay insensitive
- analog circuits
- model based diagnosis
- analog vlsi
- data sets
- digital circuits
- logic circuits
- fault model
- artificial intelligence
- test cases
- integrated circuit
- fault detection and diagnosis
- low power
- multiple faults
- knowledge base
- lateral inhibition