A topology-agnostic test model for link shorts in on-chip networks.

Biswajit Bhowmik Jatindra Kumar Deka Santosh Biswas Bhargab B. Bhattacharya

Published in: SMC (2016)

Keyphrases

conceptual model
data sets
high level
high speed
theoretical analysis
statistical model
test data
formal model
network model
real time
probabilistic model
low cost
computational model
power law