Li Li

Publication Activity (10 Years)

Years Active: 2006-2024
Publications (10 Years): 40

Top Topics

Matrix Inversion

Reconfigurable Architecture

Energy Efficiency

Top Venues

IEEE Trans. Circuits Syst. I Regul. Pap.

IEICE Electron. Express

Publications

Xinyi Li, Wenjie Fan, Heng Zhang, Jinlun Ji, Tong Cheng, Shiping Li, Li Li, Yuxiang Fu
TTNNM: Thermal- and Traffic-Aware Neural Network Mapping on 3D-NoC-based Accelerator. ACM Great Lakes Symposium on VLSI (2024)
Wenqing Song, Sirui Shen, Congwei Xu, Yilin Wang, Xinyu Wang, Yuxiang Fu, Li Li, Zhonghai Lu
Heterogeneous Reconfigurable Accelerator for Homomorphic Evaluation on Encrypted Data. IEEE Access 12 (2024)
Siyue Li, Shize Zhou, Yongqi Xue, Wenjie Fan, Tong Cheng, Jinlun Ji, Chenyang Dai, Wenqing Song, Qinyu Chen, Chang Gao, Li Li, Yuxiang Fu
HAS-RL: A Hierarchical Approximate Scheme Optimized With Reinforcement Learning for NoC-Based NN Accelerators. IEEE Trans. Circuits Syst. I Regul. Pap. 71 (4) (2024)
Yuxiang Fu, Kai Chen, Wenqing Song, Guoqiang He, Sirui Shen, Huizheng Wang, Chuan Zhang, Li Li
A DSP-Purposed REconfigurable Acceleration Machine (DREAM) for High Energy Efficiency MIMO Signal Processing. IEEE Trans. Circuits Syst. I Regul. Pap. 70 (2) (2023)
Wanyuan Hong, Hui Chen, Lianghua Quan, Yuxiang Fu, Li Li
Low-Cost High-Precision Architecture for Arbitrary Floating-Point Nth Root Computation. ISCAS (2023)
Lingxiao Zhu, Wenjie Fan, Chenyang Dai, Shize Zhou, Yongqi Xue, Zhonghai Lu, Li Li, Yuxiang Fu
A NoC-Based Spatial DNN Inference Accelerator With Memory-Friendly Dataflow. IEEE Des. Test 40 (6) (2023)
Ruiqi Wu, Hui Chen, Guoqiang He, Yuxiang Fu, Li Li
Low-Latency Low-Complexity Method and Architecture for Computing Arbitrary Nth Root of Complex Numbers. IEEE Trans. Circuits Syst. I Regul. Pap. 69 (6) (2022)
Qinyu Chen, Guoqiang He, Xinyuan Wang, Jin Xu, Sirui Shen, Hui Chen, Yuxiang Fu, Li Li
A 67.5μJ/Prediction Accelerator for Spiking Neural Networks in Image Segmentation. IEEE Trans. Circuits Syst. II Express Briefs 69 (2) (2022)
Hui Chen, Zongguang Yu, Jin Xu, Lin Jiang, Zhonghai Lu, Yuxiang Fu, Li Li
Huicore: A Generalized Hardware Accelerator for Complicated Functions. IEEE Trans. Circuits Syst. I Regul. Pap. 69 (6) (2022)
Guoqiang He, Xiaoling Ding, Minghao Zhou, Bo Liu, Li Li
Background Noise Adaptive Energy-Efficient Keywords Recognition Processor With Reusable DNN and Reconfigurable Architecture. IEEE Access 10 (2022)
Congyi Sun, Haohan Sun, Jin Xu, Jianing Han, Xinyuan Wang, Xinyu Wang, Qinyu Chen, Yuxiang Fu, Li Li
An Energy Efficient STDP-Based SNN Architecture With On-Chip Learning. IEEE Trans. Circuits Syst. I Regul. Pap. 69 (12) (2022)
Sirui Shen, Wenqing Song, Xinyu Wang, Xinyu Shao, Yuxiang Fu, Zhonghai Lu, Li Li
A Hierarchical Parallel Discrete Gaussian Sampler for Lattice-Based Cryptography. ISCAS (2022)
Yongqi Xue, Jinlun Ji, Xinyi Li, Siyue Li, Shize Zhou, Tong Cheng, Li Li, Yuxiang Fu
AOME: Autonomous Optimal Mapping Exploration Using Reinforcement Learning for NoC-based Accelerators Running Neural Networks. ICCD (2022)
Minghao Zhou, Li Li, Xiangming Fang, Rongxiang Wu
IPD capacitor with pseudo-symmetry for isolated differential signal transfer applications. Microelectron. J. 108 (2021)
Jin Xu, Lin Jiang, Hui Chen, Yuxiang Fu, Li Li
A Low-Complexity Architecture for Implementing Square to Tenth Root of Complex Numbers. ISOCC (2021)
Yuxiang Fu, Chuan Zhang, Wenqing Song, Qinyu Chen, Hui Chen, Minghao Zhou, Li Li
Optimizing Vertical Link Placement and Congestion Aware Dynamic Elevator Assignment for Partially Connected 3D-NoCs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 40 (10) (2021)
Hui Chen, Ruiqi Wu, Zhonghai Lu, Yuxiang Fu, Li Li, Zongguang Yu
A General Methodology and Architecture for Arbitrary Complex Number Nth Root Computation. ISCAS (2021)
Hui Chen, Zongguang Yu, Yonggang Zhang, Zhonghai Lu, Yuxiang Fu, Li Li
Low-Complexity High-Precision Method and Architecture for Computing the Logarithm of Complex Numbers. IEEE Trans. Circuits Syst. I Regul. Pap. 68 (8) (2021)
Qian Gao, Wenqing Song, Zhonghai Lu, Li Li, Yuxiang Fu
Dynamic and Traffic-Aware Medium Access Control Mechanisms for Wireless NoC Architectures. ISCAS (2021)
Heping Yang, Hui Chen, Yuxiang Fu, Li Li
Low-Latency Architecture for Implementing Floating-Point Multiplier and Divider Based on Symmetric-Mapping LUT. ISOCC (2021)
Hui Chen, Heping Yang, Wenqing Song, Zhonghai Lu, Yuxiang Fu, Li Li, Zongguang Yu
-Like Functions. IEEE Trans. Circuits Syst. I Regul. Pap. 68 (3) (2021)
Yonggang Zhang, Hui Chen, Yuxiang Fu, Li Li
β-softmax: A Hardware-Friendly Activation Function with Low Complexity and High Performance. ISOCC (2021)
Wenqing Song, Yifei Shen, Yuxiang Fu, Chuan Zhang, Li Li
Adaptive Successive Cancellation Priority Decoder for 5G Polar Codes. ISCAS (2021)
Hui Chen, Lin Jiang, Yuanyong Luo, Zhonghai Lu, Yuxiang Fu, Li Li, Zongguang Yu
A CORDIC-Based Architecture with Adjustable Precision and Flexible Scalability to Implement Sigmoid and Tanh Functions. ISCAS (2020)
Qinyu Chen, Yan Huang, Rui Sun, Wenqing Song, Zhonghai Lu, Yuxiang Fu, Li Li
An Efficient Accelerator for Multiple Convolutions From the Sparsity Perspective. IEEE Trans. Very Large Scale Integr. Syst. 28 (6) (2020)
Hui Chen, Kaifeng Cheng, Zhonghai Lu, Yuxiang Fu, Li Li
Hyperbolic CORDIC-Based Architecture for Computing Logarithm and Its Implementation. IEEE Trans. Circuits Syst. (11) (2020)
Wenqing Song, Yuxiang Fu, Qinyu Chen, Li Li, Chuan Zhang
ANN Based Adaptive Successive Cancellation List Decoder for Polar Codes. ASICON (2019)
Yuxiang Fu, Qinyu Chen, Guoqiang He, Kai Chen, Zhonghai Lu, Chuan Zhang, Li Li
Congestion-Aware Dynamic Elevator Assignment for Partially Connected 3D-NoCs. ISCAS (2019)
Qinyu Chen, Yuxiang Fu, Kaifeng Cheng, Wenqing Song, Zhonghai Lu, Li Li, Chuan Zhang
Smilodon: An Efficient Accelerator for Low Bit-Width CNNs with Task Partitioning. ISCAS (2019)
Yuxiang Fu, Li Li, Hongbing Pan, Kun Wang, Fan Feng, Qinyu Chen, Chuan Zhang
Thermal Sensor Placement and Thermal Reconstruction Under Gaussian and Non-Gaussian Sensor Noises for 3-D NoC. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 38 (11) (2019)
Fan Feng, Li Li, Kun Wang, Feng Han, Hongbing Pan, Wei Li
Application space exploration of a multi-fabric reconfigurable system. ASICON (2017)
Feng Han, Li Li, Kun Wang, Fan Feng, Hongbing Pan, Jin Sha, Jun Lin
An access pattern based adaptive mapping function for GPGPU scratchpad memory. IEICE Electron. Express 14 (12) (2017)
Yuxiang Fu, Li Li, Kun Wang, Chuan Zhang
Kalman Predictor-Based Proactive Dynamic Thermal Management for 3-D NoC Systems With Noisy Thermal Sensors. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 36 (11) (2017)
Kun Wang, Li Li, Feng Han, Fan Feng, Jun Lin, Yuxiang Fu, Jin Sha
Optimized sorting network for successive cancellation list decoding of polar codes. IEICE Electron. Express 14 (18) (2017)
Jun Lin, Jin Sha, Li Li, Chenrong Xiong, Zhiyuan Yan, Zhongfeng Wang
A high throughput belief propagation decoder architecture for polar codes. ISCAS (2016)
Feng Han, Li Li, Kun Wang, Fan Feng, Hongbing Pan, Baoning Zhang, Guoqiang He, Jun Lin
An ultra-long FFT architecture implemented in a reconfigurable application specified processor. IEICE Electron. Express 13 (13) (2016)
Fan Feng, Li Li, Kun Wang, Feng Han, Baoning Zhang, Guoqiang He
Floating-point operation based reconfigurable architecture for radar processing. IEICE Electron. Express 13 (21) (2016)
Yuxiang Fu, Li Li, Hongbing Pan, Kun Wang, Feng Han, Jun Lin
Accurate runtime thermal prediction scheme for 3D NoC systems with noisy thermal sensors. ISCAS (2016)
Fei Lyu, Xinfu Liu, Yinjie Ding, Eng-Huat Toh, Zhenyan Zhang, Yifan Pan, Zhen Wang, Chengjie Li, Li Li, Jin Sha, Hongbing Pan
Influences of an Aluminum Covering Layer on the Performance of Cross-Like Hall Devices. Sensors 16 (1) (2016)
Kun Wang, Li Li, Feng Han, Fan Feng, Jun Lin
Design and implementation of high performance matrix inversion based on reconfigurable processor. IEICE Electron. Express 13 (15) (2016)
Yuxiang Fu, Li Li, Yuang Zhang, Hongbing Pan, Feng Han, Kun Wang
Lateral asynchronous and vertical synchronous 3D Network on Chip with double pumped vertical links. ASICON (2015)
Feng Han, Li Li, Kun Wang, Fan Feng, Hongbing Pan, Dong Yu
An improved FFT architecture optimized for reconfigurable application specified processor. ASICON (2015)
Yuang Zhang, Li Li, Axel Jantsch, Zhonghai Lu, Minglun Gao, Yuxiang Fu, Hongbing Pan
Exploring stacked main memory architecture for 3D GPGPUs. ASICON (2015)
Kun Wang, Li Li, Feng Han, Hongbing Pan, Fan Feng, Xiao Yu
A high performance parallel VLSI design of matrix inversion. ASICON (2015)
Fei Lyu, Zhenyan Zhang, Eng-Huat Toh, Xinfu Liu, Yinjie Ding, Yifan Pan, Chengjie Li, Li Li, Jin Sha, Hongbing Pan
Performance Comparison of Cross-Like Hall Plates with Different Covering Layers. Sensors 15 (1) (2015)
Yuang Zhang, Li Li, Zhonghai Lu, Axel Jantsch, Yuxiang Fu, Minglun Gao
Performance and network power evaluation of tightly mixed SRAM NUCA for 3D Multi-core Network on Chips. ISCAS (2014)
Fei Lyu, Zhenduo Zhu, Zhenfei Lu, Li Li, Jin Sha, Hongbing Pan, Yutong Bi
A more accurate circuit model for CMOS Hall cross with non-linear resistors and JFETs. ISIC (2014)
Yuang Zhang, Li Li, Zhonghai Lu, Axel Jantsch, Minglun Gao, Hongbing Pan, Feng Han
A survey of memory architecture for 3D chip multi-processors. Microprocess. Microsystems 38 (5) (2014)
Yue Xu, Hongbing Pan, Shuzhuan He, Li Li
Monolithic H-bridge brushless DC vibration motor driver with a highly sensitive hall sensor in 0.18 μm complementary metal-oxide semiconductor technology. IET Circuits Devices Syst. 7 (4) (2013)
Xiao Yu, Li Li, Yuang Zhang, Hongbing Pan, Shuzhuan He
Performance and power consumption analysis of memory efficient 3D network-on-chip architecture. ICCA (2013)
Xiao Yu, Li Li, Yuang Zhang, Hongbing Pan, Shuzhuan He
Mass message transmission aware buffer-less packet-circuit switching router for 3D NoC. ICCA (2013)
Yue Xu, Hongbing Pan, Shuzhuan He, Li Li
A Highly Sensitive CMOS Digital Hall Sensor for Low Magnetic Field Applications. Sensors 12 (2) (2012)
Li Li, Bo Yuan, Zhongfeng Wang, Jin Sha, Hongbing Pan, Weishan Zheng
Unified Architecture for Reed-Solomon Decoder Combined With Burst-Error Correction. IEEE Trans. Very Large Scale Integr. Syst. 20 (7) (2012)
Jiawen Wang, Li Li, Hongbing Pan, Shuzhuan He, Rong Zhang
Latency-aware mapping for 3D NoC using rank-based multi-objective genetic algorithm. ASICON (2011)
Jun Lin, Jin Sha, Zhongfeng Wang, Li Li
Efficient Decoder Design for Nonbinary Quasicyclic LDPC Codes. IEEE Trans. Circuits Syst. I Regul. Pap. (5) (2010)
Shuai Zhou, Jin Sha, Li Li, Zhongfeng Wang
Layered decoding for non-binary LDPC codes. ISCAS (2010)
Kai He, Jin Sha, Li Li, Zhongfeng Wang
Low power decoder design for QC-LDPC codes. ISCAS (2010)
Jun Lin, Jin Sha, Zhongfeng Wang, Li Li
An Efficient VLSI Architecture for Nonbinary LDPC Decoders. IEEE Trans. Circuits Syst. II Express Briefs (1) (2010)
Wei Yi, Hongbing Pan, Peng Pan, Li Li, Minglun Gao, Ning Hou, Gaoming Du, Duoli Zhang
Application-level pipelining on Hierarchical NoC. ISCAS (2010)
Chuan Zhang, Zhongfeng Wang, Jin Sha, Li Li, Jun Lin
Flexible LDPC Decoder Design for Multigigabit-per-Second Applications. IEEE Trans. Circuits Syst. I Regul. Pap. (1) (2010)
Bo Yuan, Li Li, Zhongfeng Wang
High-speed area-efficient versatile Reed-Solomon decoder design for multi-mode applications. SiPS (2009)
Bo Yuan, Zhongfeng Wang, Li Li, Minglun Gao, Jin Sha, Chuan Zhang
Area-efficient reed-solomon decoder design for optical communications. IEEE Trans. Circuits Syst. II Express Briefs (6) (2009)
Jin Sha, Zhongfeng Wang, Minglun Gao, Li Li
Multi-Gb/s LDPC Code Design and Implementation. IEEE Trans. Very Large Scale Integr. Syst. 17 (2) (2009)
Jin Sha, Jun Lin, Zhongfeng Wang, Li Li, Minglun Gao
LDPC decoder design for high rate wireless personal area networks. IEEE Trans. Consumer Electron. 55 (2) (2009)
Jun Lin, Jin Sha, Zhongfeng Wang, Li Li
An improved min-sum based column-layered decoding algorithm for LDPC codes. SiPS (2009)
Zhigang Wu, Jin Sha, Zhongfeng Wang, Li Li, Minglun Gao
An improved scaled DCT architecture. IEEE Trans. Consumer Electron. 55 (2) (2009)
Jin Sha, Jun Lin, Li Li, Minglun Gao, Zhongfeng Wang
LDPC Decoder Design for IEEE 802.15 Standard. ISCAS (2009)
Jinjin He, Zhongfeng Wang, Zhiqiang Cui, Li Li
Towards an Optimal Trade-off of Viterbi Decoder Design. ISCAS (2009)
Bo Yuan, Li Li, Jin Sha, Zhongfeng Wang
Area-efficient Reed-Solomon Decoder Design for 10-100 Gb/s Applications. ISCAS (2009)
Chuan Zhang, Li Li, Jun Xu, Zhongfeng Wang
High-throughput GCM VLSI Architecture for IEEE 802.1ae Applications. ISCAS (2009)
Jun Lin, Zhongfeng Wang, Li Li, Jin Sha, Minglun Gao
Efficient Shuffle Network Architecture and Application for WiMAX LDPC Decoders. IEEE Trans. Circuits Syst. II Express Briefs (3) (2009)
Jin Sha, Jun Lin, Zhongfeng Wang, Li Li, Minglun Gao
Decoder Design for RS-Based LDPC Codes. IEEE Trans. Circuits Syst. II Express Briefs (9) (2009)
Li Li, Yong-Sheng Yin, Minglun Gao
Mapping algorithms of MIMO to a Multi-Pipeline Reconfigurable System. APCCAS (2008)
Chuan Zhang, Li Li, Jun Lin, Zhongfeng Wang
Low-complexity shift-LDPC decoder for high-speed communication systems. APCCAS (2008)
Yuang Zhang, Li Li, Shengguang Yang, Lan Dong, Xiaoxiang Lou, Minglun Gao
A scalable distributed memory architecture for Network on Chip. APCCAS (2008)
Yong-Sheng Yin, Li Li, Minglun Gao, Gaoming Du, Yu-Kun Song
On the Implementation of Virtual Array Using Configuration Plane. APPT (2007)
Jin Sha, Minglun Gao, Zhongjin Zhang, Li Li, Zhongfeng Wang
An FPGA Implementation of Array LDPC Decoder. APCCAS (2006)