An Efficient VLSI Architecture for Nonbinary LDPC Decoders.

Jun Lin Jin Sha Zhongfeng Wang Li Li

Published in: IEEE Trans. Circuits Syst. II Express Briefs (2010)

Keyphrases

decoding algorithm
low density parity check
non binary
vlsi architecture
ldpc codes
constraint satisfaction problems
vlsi implementation
low power
low complexity
real time
arc consistency
high speed
video sequences
noise model
power consumption
channel coding
generative model
low cost
mining high utility itemsets