Yong-Sheng Yin

Publication Activity (10 Years)

Years Active: 2007-2022
Publications (10 Years): 11

Top Topics

Hardware Architecture

Top Venues

IEICE Electron. Express

Publications

XiMing Xie, Hongmei Chen, Yong-Sheng Yin, Jian Wang, Long Li, Honghui Deng, Xu Meng
All-digital calibration algorithm based on channel multiplexing for TI-ADCs. Microelectron. J. 126 (2022)
Shijie Hu, Gaoming Du, Jiashen Li, Zhenmin Li, Wei Ni, Yong-Sheng Yin, Xiaolei Wang
Optimization of Node-clustering-based DAG partition targeting NVDLA Architecture. ASICON (2021)
Hongmei Chen, Yong-Sheng Yin, Tao Liu, Linhao Gan, Rui Xiao, Hui Yan, Honghui Deng
A split-based fully digital feedforward background calibration technique for timing mismatch in TIADC. Integr. 71 (2020)
Yong-Sheng Yin, Kangkang Sun, Hongmei Chen, Xiaolei Wang, Lu Liu, Honghui Deng, Xu Meng, Kun Li, Zhongfeng Wang
Calibration of timing mismatch in TIADC based on monotonicity detecting of sampled data. IEICE Electron. Express 17 (3) (2020)
Gaoming Du, Zhenwen Yang, Zhenmin Li, Duoli Zhang, Yong-Sheng Yin, Zhonghai Lu
NR-MPA: Non-Recovery Compression Based Multi-Path Packet-Connected-Circuit Architecture of Convolution Neural Networks Accelerator. ICCD (2019)
Gaoming Du, Chao Tian, Zhenmin Li, Duoli Zhang, Yong-Sheng Yin, Yiming Ouyang
Efficient Softmax Hardware Architecture for Deep Neural Networks. ACM Great Lakes Symposium on VLSI (2019)
Yong-Sheng Yin, Liu Liu, Hongmei Chen, Honghui Deng, Xu Meng, Jing-Sheng Wu, Zhongfeng Wang
A channel multiplexing digital calibration technique for timing mismatch of time-interleaved ADCs. IEICE Electron. Express 16 (19) (2019)
Xu Meng, Yong-Sheng Yin, Jinzhao Han
A Low Noise Sub-Gigahertz Fractional-N Frequency Generator with Cascaded FIR. J. Circuits Syst. Comput. 28 (3) (2019)
Hongmei Chen, Yunsheng Pan, Yong-Sheng Yin, Fujiang Lin
All-digital background calibration technique for timing mismatch of time-interleaved ADCs. Integr. 57 (2017)
Hongmei Chen, Maochen Jian, Yong-Sheng Yin, Fujiang Lin, Qing Cui
An efficient digital calibration technique for timing mismatch in time-interleaved ADCs. IEICE Electron. Express 13 (13) (2016)
Hongmei Chen, Yong-Sheng Yin, Honghui Deng, Fujiang Lin
A Low Complexity All-Digital Background Calibration Technique for Time-Interleaved ADCs. VLSI Design 2016 (2016)
Guangfa Si, Yong-Sheng Yin, Honghui Deng
Design of a novel high-accuracy LED driving chip. ASICON (2015)
Yong-Sheng Yin, Rui Zhang, Jun Yang, Minglun Gao
Calibration method considering second-order error term of timing skew for a novel multi-channel ADC. ASICON (2011)
Mei Jiao, Yong-Sheng Yin, Shangquan Liang, Honghui Deng
On the design of a power conversion circuit. APCCAS (2008)
Shangquan Liang, Minglun Gao, Yong-Sheng Yin, Honghui Deng
A 14-bit 320 MSPS Segmented Current-Steering D/A Converter for High-Speed Applications. DELTA (2008)
Li Li, Yong-Sheng Yin, Minglun Gao
Mapping algorithms of MIMO to a Multi-Pipeline Reconfigurable System. APCCAS (2008)
Yong-Sheng Yin, Gaoming Du, Yu-Kun Song
Study on the Multi-pipeline Reconfigurable Computing System. CSSE (4) (2008)
Shangquan Liang, Yong-Sheng Yin, Honghui Deng, Yu-Kun Song, Minglun Gao
A low power consumption, high speed Op-amp for a 10-bit 100MSPS parallel pipeline ADC. APCCAS (2008)
Yong-Sheng Yin, Li Li, Minglun Gao, Gaoming Du, Yu-Kun Song
On the Implementation of Virtual Array Using Configuration Plane. APPT (2007)