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Feng Han
Publication Activity (10 Years)
Years Active: 2014-2017
Publications (10 Years): 7
Top Topics
Reconfigurable Architecture
Embedded Dram
Systolic Array
Network On Chip
Top Venues
IEICE Electron. Express
ASICON
Microprocess. Microsystems
ISCAS
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Publications
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Fan Feng
,
Li Li
,
Kun Wang
,
Feng Han
,
Hongbing Pan
,
Wei Li
Application space exploration of a multi-fabric reconfigurable system.
ASICON
(2017)
Feng Han
,
Li Li
,
Kun Wang
,
Fan Feng
,
Hongbing Pan
,
Jin Sha
,
Jun Lin
An access pattern based adaptive mapping function for GPGPU scratchpad memory.
IEICE Electron. Express
14 (12) (2017)
Kun Wang
,
Li Li
,
Feng Han
,
Fan Feng
,
Jun Lin
,
Yuxiang Fu
,
Jin Sha
Optimized sorting network for successive cancellation list decoding of polar codes.
IEICE Electron. Express
14 (18) (2017)
Feng Han
,
Li Li
,
Kun Wang
,
Fan Feng
,
Hongbing Pan
,
Baoning Zhang
,
Guoqiang He
,
Jun Lin
An ultra-long FFT architecture implemented in a reconfigurable application specified processor.
IEICE Electron. Express
13 (13) (2016)
Fan Feng
,
Li Li
,
Kun Wang
,
Feng Han
,
Baoning Zhang
,
Guoqiang He
Floating-point operation based reconfigurable architecture for radar processing.
IEICE Electron. Express
13 (21) (2016)
Yuxiang Fu
,
Li Li
,
Hongbing Pan
,
Kun Wang
,
Feng Han
,
Jun Lin
Accurate runtime thermal prediction scheme for 3D NoC systems with noisy thermal sensors.
ISCAS
(2016)
Kun Wang
,
Li Li
,
Feng Han
,
Fan Feng
,
Jun Lin
Design and implementation of high performance matrix inversion based on reconfigurable processor.
IEICE Electron. Express
13 (15) (2016)
Yuxiang Fu
,
Li Li
,
Yuang Zhang
,
Hongbing Pan
,
Feng Han
,
Kun Wang
Lateral asynchronous and vertical synchronous 3D Network on Chip with double pumped vertical links.
ASICON
(2015)
Feng Han
,
Li Li
,
Kun Wang
,
Fan Feng
,
Hongbing Pan
,
Dong Yu
An improved FFT architecture optimized for reconfigurable application specified processor.
ASICON
(2015)
Kun Wang
,
Li Li
,
Feng Han
,
Hongbing Pan
,
Fan Feng
,
Xiao Yu
A high performance parallel VLSI design of matrix inversion.
ASICON
(2015)
Yuang Zhang
,
Li Li
,
Zhonghai Lu
,
Axel Jantsch
,
Minglun Gao
,
Hongbing Pan
,
Feng Han
A survey of memory architecture for 3D chip multi-processors.
Microprocess. Microsystems
38 (5) (2014)