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Floating-point operation based reconfigurable architecture for radar processing.
Fan Feng
Li Li
Kun Wang
Feng Han
Baoning Zhang
Guoqiang He
Published in:
IEICE Electron. Express (2016)
Keyphrases
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floating point
reconfigurable architecture
fixed point
square root
systolic array
low cost
sparse matrices
parallel architecture
signal processing
instruction set
floating point arithmetic
image processing
pairwise