A scalable distributed memory architecture for Network on Chip.
Yuang ZhangLi LiShengguang YangLan DongXiaoxiang LouMinglun GaoPublished in: APCCAS (2008)
Keyphrases
- multi processor
- network on chip
- distributed memory
- shared memory
- single processor
- program execution
- parallel architecture
- parallel implementation
- parallel computers
- multi core processors
- ibm sp
- message passing
- parallel algorithm
- parallel computing
- parallel machines
- lower bound
- pairwise
- parallel programming
- computational complexity
- routing algorithm