Low power decoder design for QC-LDPC codes.

Kai He Jin Sha Li Li Zhongfeng Wang

Published in: ISCAS (2010)

Keyphrases

low power
low density parity check
ldpc codes
low cost
power consumption
high speed
low power consumption
vlsi architecture
error correction
decoding algorithm
power dissipation
message passing
channel coding
low complexity
ultra low power
real time
rate allocation
motion estimation