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Low-Latency Architecture for Implementing Floating-Point Multiplier and Divider Based on Symmetric-Mapping LUT.
Heping Yang
Hui Chen
Yuxiang Fu
Li Li
Published in:
ISOCC (2021)
Keyphrases
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floating point
low latency
instruction set
floating point arithmetic
real time
fixed point
high bandwidth
high speed
high throughput
highly efficient
virtual machine
stream processing
probabilistic model