Zhiqiang Cui

Publication Activity (10 Years)

Years Active: 2006-2024
Publications (10 Years): 2

Top Topics

Data Assimilation

Error Correcting

Top Venues

Publications

Zhiqiang Cui, Hongli Jia, Qi Gao, Haowen Song
Maintenance Spare Parts Prediction Based on Multilevel Migration Learning CNN-ISE-Attention-BiLSTM. IEEE Access 12 (2024)
Zhiqiang Cui, Zhaoxia Pu
The Use of Regional Data Assimilation to Improve Numerical Simulations of Diurnal Characteristics of Precipitation during an Active Madden-Julian Oscillation Event over the Maritime Continent. Remote. Sens. 15 (9) (2023)
Zhiqiang Cui, Zhongfeng Wang, Xinming Huang
Multilevel error correction scheme for MLC flash memory. ISCAS (2014)
Zhiqiang Cui, Zhongfeng Wang, Xinmiao Zhang
Reduced-Complexity Column-Layered Decoding and Implementation for LDPC Codes CoRR (2012)
Zhiqiang Cui, Zhongfeng Wang, Xinmiao Zhang
Reduced-complexity column-layered decoding and implementation for LDPC codes. IET Commun. 5 (15) (2011)
Zhiqiang Cui, Zhongfeng Wang, Youjian Liu
High-Throughput Layered LDPC Decoding Architecture. IEEE Trans. Very Large Scale Integr. Syst. 17 (4) (2009)
Jinjin He, Zhongfeng Wang, Zhiqiang Cui, Li Li
Towards an Optimal Trade-off of Viterbi Decoder Design. ISCAS (2009)
Zhiqiang Cui, Zhongfeng Wang, Xinmiao Zhang, Qingwei Jia
Efficient decoder design for high-throughput LDPC decoding. APCCAS (2008)
Zhiqiang Cui, Zhongfeng Wang
Improved low-complexity low-density parity-check decoding. IET Commun. 2 (8) (2008)
Zhiqiang Cui, Zhongfeng Wang
Extended layered decoding of LDPC codes. ACM Great Lakes Symposium on VLSI (2008)
Zhiqiang Cui, Zhongfeng Wang
Efficient Message Passing Architecture for High Throughput LDPC Decoder. ISCAS (2007)
Zhongfeng Wang, Zhiqiang Cui
Low-Complexity High-Speed Decoder Design for Quasi-Cyclic LDPC Codes. IEEE Trans. Very Large Scale Integr. Syst. 15 (1) (2007)
Zhiqiang Cui, Zhongfeng Wang
Studies on Practical Low Complexity Decoding of Low-Density Parity-Check Codes. SiPS (2007)
Zhongfeng Wang, Zhiqiang Cui
A Memory Efficient Partially Parallel Decoder Architecture for Quasi-Cyclic LDPC Codes. IEEE Trans. Very Large Scale Integr. Syst. 15 (4) (2007)
Zhiqiang Cui, Zhongfeng Wang
A 170 Mbps (8176, 7156) quasi-cyclic LDPC decoder implementation with FPGA. ISCAS (2006)
Zhiqiang Cui, Zhongfeng Wang
Area-efficient parallel decoder architecture for high rate QC-LDPC codes. ISCAS (2006)