A 170 Mbps (8176, 7156) quasi-cyclic LDPC decoder implementation with FPGA.
Zhiqiang CuiZhongfeng WangPublished in: ISCAS (2006)
Keyphrases
- fpga implementation
- hardware implementation
- high speed
- low cost
- ldpc codes
- dedicated hardware
- signal processing
- field programmable gate array
- distributed video coding
- fpga hardware
- vlsi architecture
- turbo codes
- decoding algorithm
- software implementation
- hardware architecture
- parallel architecture
- hardware design
- reconfigurable hardware
- hardware architectures
- low complexity