James B. Kuo

Publication Activity (10 Years)

Years Active: 1989-2014
Publications (10 Years): 0

Top Topics

Power Consumption

Delay Insensitive

Top Venues

Publications

C. B. Hsu, James B. Kuo
Power consumption optimization methodology (PCOM) for low-power/ low-voltage 32-bit microprocessor circuit design via MTCMOS. MWSCAS (2014)
C. B. Hsu, Young Sik Hong, James B. Kuo
MTCMOS low-power optimization technique (LPOT) for 1V pipelined RISC CPU circuit. ICECS (2014)
Gregory J. Y. Lin, Chienbo B. Hsu, James B. Kuo
Critical-path aware power consumption optimization methodology (CAPCOM) using mixed-VTH cells for low-power SOC designs. ISCAS (2014)
C. B. Hsu, James B. Kuo
MTCMOS low-power design technique (LPDT) for low-voltage pipelined microprocessor circuits. ISIC (2014)
Henry X. F. Huang, Steven R. S. Shen, James B. Kuo
Cell-Based Leakage Power Reduction Priority (CBLPRP) Optimization Methodology for Designing SOC Applications Using MTCMOS Technique. PATMOS (2011)
Chih-Hsiang Lin, James B. Kuo
Low-voltage SOI CMOS DTMOS/MTCMOS circuit technique for design optimization of low-power SOC applications. ISCAS (2010)
Chih-Hsiang Lin, James B. Kuo
Design Optimization of Low-Power 90nm CMOS SOC Application Using 0.5V Bulk PMOS Dynamic-Threshold with Dual Threshold (MTCMOS): BP-DTMOS-DT Technique. PATMOS (2009)
Harry I. A. Chen, Edward K. W. Loo, James B. Kuo, Marek Syrzycki
Triple-Threshold Static Power Minimization in High-Level Synthesis of VLSI CMOS. PATMOS (2007)
James B. Kuo
Evolution of Bootstrap Techniques in Low-Voltage CMOS Digital VLSI Circuits for SoC Applications, invited. IWSOC (2005)
Hung-Pin Chen, James B. Kuo
A 0.8 V CMOS TSPC adiabatic DCVS logic circuit with the bootstrap technique for low-power VLSI. ICECS (2004)
P. C. Chen, James B. Kuo
Novel sub-1V CMOS domino dynamic logic circuit using a direct bootstrap (DB) technique for low-voltage CMOS VLSI. ISCAS (5) (2003)
Perng-Fei Lin, James B. Kuo
A 0.8-V 128-kb four-way set-associative two-level CMOS cache memory using two-stage wordline/bitline-oriented tag-compare (WLOTC/BLOTC) scheme. IEEE J. Solid State Circuits 37 (10) (2002)
S. C. Liu, F. A. Wu, James B. Kuo
A novel low-voltage content-addressable-memory (CAM) cell with a fast tag-compare capability using partially depleted (PD) SOI CMOS dynamic-threshold (DTMOS) techniques. IEEE J. Solid State Circuits 36 (4) (2001)
Perng-Fei Lin, James B. Kuo
A 1-V 128-kb four-way set-associative CMOS cache memory using wordline-oriented tag-compare (WLOTC) structure with the content-addressable-memory (CAM) 10-transistor tag cell. IEEE J. Solid State Circuits 36 (4) (2001)
Bo-Ting Wang, James B. Kuo
A novel two-port 6T CMOS SRAM cell structure for low-voltage VLSI SRAM with single-bit-line simultaneous read-and-write access (SBLSRWA) capability. ISCAS (2000)
J. H. Lou, James B. Kuo
1.5 V CMOS bootstrapped dynamic logic circuit techniques (BDLCT) suitable for low-voltage deep-submicron CMOS VLSI for implementing 482 MHz digital quadrature modulator and adder. ICECS (1998)
J. H. Lou, James B. Kuo
A 1.5-V full-swing bootstrapped CMOS large capacitive-load driver circuit suitable for low-voltage CMOS VLSI. IEEE J. Solid State Circuits 32 (1) (1997)
Y. G. Chen, James B. Kuo
A unified triode/saturation model with an improved continuity in the output conductance suitable for CAD of VLSI circuits using deep sub-0.1 µm NMOS devices. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 15 (2) (1996)
James B. Kuo, K. W. Su, J. H. Lou
A BiCMOS dynamic multiplier using Wallace tree reduction architecture and 1.5-V full-swing BiCMOS dynamic logic circuit. IEEE J. Solid State Circuits 30 (8) (1995)
James B. Kuo, K. W. Su, J. H. Lou, S. S. Chen, C. S. Chiang
A 1.5 V full-swing BiCMOS dynamic logic gate circuit suitable for VLSI using low-voltage BiCMOS technology. IEEE J. Solid State Circuits 30 (1) (1995)
James B. Kuo, B. Y. Chen, Mark W. Mao
A Radical-Partitioned Neural Network System Using a Modified Sigmoid Function and a Wight-Dotted Radical Selector for Large-Volume Chinese Characters Recognition VLSI. ISCAS (1994)
James B. Kuo, K. W. Su, J. H. Lou
A BiCMOS Dynamic Multiplier Using Wallace Tree Reduction Architecture and 1.5V Full-Swing BiCMOS Dynamic Logic Circuit. ISCAS (1994)
Mark W. Mao, B. Y. Chen, James B. Kuo
A Coded Block Neural Network System Suitable for VLSI Implementation Using an Adaptive Learning-rate Epoch-based Back Propagation Technique. ISCAS (1993)
James B. Kuo, Hung-Pin Chen, H. J. Huang
A BiCMOS Dynamic Divider Circuit Using a Restoring Iterative Architecture with Carry Look Ahead for CPU VLSI. ISCAS (1993)
H.-C. Chow, W.-S. Feng, James B. Kuo
An improved analytical short-channel MOSFET model valid in all regions of operating for analog/digital circuit simulation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 11 (12) (1992)
Mark W. Mao, James B. Kuo
A coded block adaptive neural network system with a radical-partitioned structure for large-volume Chinese characters recognition. Neural Networks 5 (5) (1992)
James B. Kuo, G. P. Rosseel, Robert W. Dutton
Two-dimensional analysis of a merged BiPMOS device. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 8 (8) (1989)
James B. Kuo, Tsen-Shau Yang, Robert W. Dutton, Bruce A. Wooley
Two-dimensional transient analysis of a collector-up ECL inverter. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 8 (10) (1989)