Login / Signup

A 0.8-V 128-kb four-way set-associative two-level CMOS cache memory using two-stage wordline/bitline-oriented tag-compare (WLOTC/BLOTC) scheme.

Perng-Fei LinJames B. Kuo
Published in: IEEE J. Solid State Circuits (2002)
Keyphrases
  • knowledge base
  • garbage collection
  • neural network
  • query processing
  • small number
  • main memory
  • associative memory