Perng-Fei Lin

Publication Activity (10 Years)

Years Active: 2001-2002
Publications (10 Years): 0

Publications

Perng-Fei Lin, James B. Kuo
A 0.8-V 128-kb four-way set-associative two-level CMOS cache memory using two-stage wordline/bitline-oriented tag-compare (WLOTC/BLOTC) scheme. IEEE J. Solid State Circuits 37 (10) (2002)
Perng-Fei Lin, James B. Kuo
A 1-V 128-kb four-way set-associative CMOS cache memory using wordline-oriented tag-compare (WLOTC) structure with the content-addressable-memory (CAM) 10-transistor tag cell. IEEE J. Solid State Circuits 36 (4) (2001)