Triple-Threshold Static Power Minimization in High-Level Synthesis of VLSI CMOS.
Harry I. A. ChenEdward K. W. LooJames B. KuoMarek SyrzyckiPublished in: PATMOS (2007)
Keyphrases
- high level synthesis
- power consumption
- power dissipation
- chip design
- vlsi circuits
- high speed
- low power
- single chip
- signal processing
- parallel architecture
- cmos technology
- design space exploration
- objective function
- image processing
- low cost
- focal plane
- vlsi design
- power distribution
- power management
- mixed signal
- real world
- parallel processing