Login / Signup
A BiCMOS Dynamic Multiplier Using Wallace Tree Reduction Architecture and 1.5V Full-Swing BiCMOS Dynamic Logic Circuit.
James B. Kuo
K. W. Su
J. H. Lou
Published in:
ISCAS (1994)
Keyphrases
</>
dynamic logic
mixed signal
dynamic environments
hardware implementation
imperative programs
analog vlsi
multi channel
real time
cmos technology
management system
artificial intelligence
parallel processing
low power
floating point
digital circuits
tree structure
high speed
propositional dynamic logic