Critical-path aware power consumption optimization methodology (CAPCOM) using mixed-VTH cells for low-power SOC designs.
Gregory J. Y. LinChienbo B. HsuJames B. KuoPublished in: ISCAS (2014)
Keyphrases
- low power
- power consumption
- critical path
- nm technology
- high speed
- low power consumption
- power saving
- energy efficiency
- job shop scheduling problem
- low cost
- power management
- single chip
- digital signal processing
- power reduction
- vlsi architecture
- optimization problems
- energy saving
- image sensor
- cmos technology
- power dissipation
- design methodology
- combinatorial optimization
- ultra low power