Design Optimization of Low-Power 90nm CMOS SOC Application Using 0.5V Bulk PMOS Dynamic-Threshold with Dual Threshold (MTCMOS): BP-DTMOS-DT Technique.
Chih-Hsiang LinJames B. KuoPublished in: PATMOS (2009)
Keyphrases
- low power
- power consumption
- high speed
- low cost
- cmos technology
- ultra low power
- wireless transmission
- single chip
- high power
- nm technology
- power reduction
- digital signal processing
- real time
- image sensor
- logic circuits
- power dissipation
- belief propagation
- mixed signal
- gate array
- back propagation
- vlsi architecture
- low power consumption
- delay insensitive