MTCMOS low-power optimization technique (LPOT) for 1V pipelined RISC CPU circuit.
C. B. HsuYoung Sik HongJames B. KuoPublished in: ICECS (2014)
Keyphrases
- low power
- low power consumption
- high speed
- logic circuits
- cmos technology
- power reduction
- power consumption
- power dissipation
- low cost
- gate array
- delay insensitive
- vlsi circuits
- single chip
- mixed signal
- application specific
- high power
- wireless transmission
- nm technology
- digital signal processing
- vlsi architecture
- data flow
- instruction set
- multithreading
- low voltage
- circuit design