Fule Li

Publication Activity (10 Years)

Years Active: 2006-2024
Publications (10 Years): 41

Top Topics

Differential Equations

Cmos Technology

Error Reduction

Top Venues

Publications

Hailong Xing, Yonggui Kao, Guangbin Wang, Fule Li
Corrigendum to 'Distributed sliding mode control for a class of impulsive uncertain delayed partial differential equations via sliding mode compensator approach' [European Journal of Control 77 (2024) 100984]. Eur. J. Control 78 (2024)
Chen Chen, Fangzhen Jiang, Peng Wang, Yongli Chen, Yan Xiao, Fule Li, Xiang Xie
A Reconfigurable Continuous-Time Delta-Sigma Modulator Structure Using Hybrid Loop Filter and Time-Interleaved Quantizer. ISCAS (2024)
Peilin Yang, Fule Li, Zhihua Wang
A 14-Bit 4 GS/s Two-Way Interleaved Pipelined ADC With Aperture Error Tunning. IEEE Trans. Circuits Syst. II Express Briefs 71 (6) (2024)
Hailong Xing, Yonggui Kao, Guangbin Wang, Fule Li
Distributed sliding mode control for a class of impulsive uncertain delayed partial differential equations via sliding mode compensator approach. Eur. J. Control 77 (2024)
Yaning Wang, Zhenguo Li, Peng Wang, Yihang Cheng, Fule Li, Yi Hu, Jiali Hou, Meng Su, Mengjiao Li
A Floating-Ring Hybrid Amplifier Insensitive to PVT and Common-mode Variation without CMFB for High-Speed ADCs. ISCAS (2024)
Junjie Jing, Yang Ding, Lingxiao Shen, Peng Wang, Fule Li
A Wide Input Common-mode Range Pipelined ADC Front-end with Common-mode Refreshing. NEWCAS (2023)
Zhiqiang Luo, Peng Wang, Jingpeng Zhou, Fule Li
All-Digital Background Calibration of a Pipelined-SAR ADC Using the "Split ADC" Architecture. ISCAS (2023)
Yaoyu Li, Yanshu Guo, Wen Jia, Fule Li, Zhihua Wang, Hanjun Jiang
Current-Steering DAC Calibration Using Q-Learning. ISCAS (2023)
Yihang Cheng, Yaning Wang, Fule Li, Chun Zhang, Zhihua Wang
High Linearity Front-End Circuit for RF Sampling ADCs with Nonlinear Junction Capacitor Cancellation. ISCAS (2023)
Yaning Wang, Yihang Cheng, Yongli Chen, Fule Li, Chun Zhang, Zhihua Wang
A Low Noise High Speed Dynamic Comparator Insensitive to PVT and Common-mode Input. NEWCAS (2023)
Haoran Wang, Junjie Jing, Fule Li
A Self-Regulating Negative Charge Pump Using Multi-Phase Clock for Wideband ADCs. ISCAS (2022)
Zhiqiang Luo, Peng Wang, Fule Li, Chun Zhang, Zhihua Wang
A statistics-based background capacitor mismatch calibration algorithm for SAR ADC. ICTA (2022)
Meng Ni, Xiao Wang, Fule Li, Woogeun Rhee, Zhihua Wang
A 13-Bit 2-GS/s Time-Interleaved ADC With Improved Correlation-Based Timing Skew Calibration Strategy. IEEE Trans. Circuits Syst. I Regul. Pap. 69 (2) (2022)
Haoran Wang, Fule Li
A 12-bit 800MS/s pipelined A/D converter. ASICON (2021)
Peilin Yang, Fule Li, Zhihua Wang
A 12-Bit 2-GS/s Pipelined ADC Front-End Stage with Aperture Error Tuning and Split MDAC. ISCAS (2021)
Meng Ni, Xiao Wang, Fule Li, Zhihua Wang
A 13-bit 312.5-MS/s Pipelined SAR ADC With Open-Loop Integrator-Based Residue Amplifier and Gain-Stabilized Integration Time Generation. IEEE Trans. Very Large Scale Integr. Syst. 29 (7) (2021)
Xiao Wang, Fule Li, Zhihua Wang
A Simple Histogram-Based Capacitor Mismatch Calibration in SAR ADCs. IEEE Trans. Circuits Syst. (12) (2020)
Meng Ni, Xiao Wang, Zhe Zhou, Yang Ding, Fule Li, Woogeun Rhee, Zhihua Wang
A 13-bit 312.5-MS/s Pipelined SAR ADC with Integrator-type Residue Amplifier and Inter-stage Gain Stabilization Technique. MWSCAS (2020)
Shaoquan Gao, Hanjun Jiang, Fule Li, Zhihua Wang
A 530 nA quiescent current low-dropout regulator with embedded reference for wake-up receivers. Sci. China Inf. Sci. 63 (12) (2020)
Meng Ni, Xiao Wang, Zhe Zhou, Yang Ding, Fule Li, Woogeun Rhee, Zhihua Wang
A Correlation-based Timing Skew Calibration Strategy Using a Time-Interleaved Reference ADC. MWSCAS (2020)
Peilin Yang, Xiao Wang, Chengwei Wang, Fule Li, Hanjun Jiang, Zhihua Wang
A 14-bit 200-Ms/s SHA-Less Pipelined ADC With Aperture Error Reduction. IEEE Trans. Very Large Scale Integr. Syst. 28 (9) (2020)
Shaoquan Gao, Hanjun Jiang, Fule Li, Zhihua Wang
DCO gain calibration technique in fractional-N Δ-Σ PLL based two-point phase modulators. MWSCAS (2019)
Xiao Wang, Fule Li, Wen Jia, Zhihua Wang
A 14-Bit 500-MS/s Time-Interleaved ADC With Autocorrelation-Based Time Skew Calibration. IEEE Trans. Circuits Syst. II Express Briefs (2) (2019)
Zhaoyang Weng, Hanjun Jiang, Jingjing Dong, Yang Li, Jingyi Zheng, Yiyu Shen, Fule Li, Woogeun Rhee, Zhihua Wang
400-MHz/2.4-GHz Combo WPAN Transceiver IC for Simultaneous Dual-Band Communication With One Single Antenna. IEEE Trans. Circuits Syst. I Regul. Pap. (2) (2018)
Chengwei Wang, Xiao Wang, Yang Ding, Fule Li, Zhihua Wang
A 14-bit 250MS/s Low-Power Pipeline ADC with Aperture Error Eliminating Technique. ISCAS (2018)
Xiao Wang, Chengwei Wang, Fule Li, Zhihua Wang
A Low-Power 12-bit 2GS/s Time-Interleaved Pipelined-SAR ADC in 28nm CMOS Process. ISCAS (2018)
Xuqiang Zheng, Chun Zhang, Fangxu Lv, Feng Zhao, Shigang Yue, Ziqiang Wang, Fule Li, Hanjun Jiang, Zhihua Wang
A 4-40 Gb/s PAM4 transmitter with output linearity optimization in 65 nm CMOS. CICC (2017)
Jingjing Dong, Hanjun Jiang, Kai Yang, Zhaoyang Weng, Fule Li, Jianjun Wei, Yanqing Ning, Xinkai Chen, Zhihua Wang
A Wireless Body Sound Sensor with a Dedicated Compact Chipset. Circuits Syst. Signal Process. 36 (6) (2017)
Ruihan Pei, Jia Liu, Xian Tang, Fule Li, Zhihua Wang
A low-offset dynamic comparator with input offset-cancellation. ASICON (2017)
Weitao Li, Fule Li, Jia Liu, Hongyu Li, Zhihua Wang
A 13-bit 160MS/s pipelined subranging-SAR ADC with low-offset dynamic comparator. A-SSCC (2017)
Honghao Chu, Fule Li
A 14bit 320MS/s pipelined-SAR ADC based on multiplexing of dynamic amplifier. ASICON (2017)
Xuqiang Zheng, Fangxu Lv, Feng Zhao, Shigang Yue, Chun Zhang, Ziqiang Wang, Fule Li, Hanjun Jiang, Zhihua Wang
A 10 GHz 56 fsrms-integrated-jitter and -247 dB FOM ring-VCO based injection-locked clock multiplier with a continuous frequency-tracking loop in 65 nm CMOS. CICC (2017)
Xuqiang Zheng, Chun Zhang, Fangxu Lv, Feng Zhao, Shuai Yuan, Shigang Yue, Ziqiang Wang, Fule Li, Zhihua Wang, Hanjun Jiang
A 40-Gb/s Quarter-Rate SerDes Transmitter and Receiver Chipset in 65-nm CMOS. IEEE J. Solid State Circuits 52 (11) (2017)
Xuqiang Zheng, Chun Zhang, Fangxu Lv, Feng Zhao, Shigang Yue, Ziqiang Wang, Fule Li, Zhihua Wang
A 5-50 Gb/s quarter rate transmitter with a 4-tap multiple-MUX based FFE in 65 nm CMOS. ESSCIRC (2016)
Xiao Wang, Fule Li, Zhihua Wang
A novel autocorrelation-based timing mismatch C alibration strategy in Time-Interleaved ADCs. ISCAS (2016)
Xuqiang Zheng, Chun Zhang, Shuai Yuan, Feng Zhao, Shigang Yue, Ziqiang Wang, Fule Li, Zhihua Wang
An improved 40 Gb/s CDR with jitter-suppression filters and phase-compensating interpolators. A-SSCC (2016)
Zhaoming Wu, Chun Zhang, Fule Li, Zhihua Wang
High speed serial interface transceiver controller based on JESD204B. NEWCAS (2016)
Naiwen Zhou, Linghan Wu, Ziqiang Wang, Xuqiang Zheng, Weidong Cao, Chun Zhang, Fule Li, Zhihua Wang
A 28-Gb/s transmitter with 3-tap FFE and T-coil enhanced terminal in 65-nm CMOS technology. NEWCAS (2016)
Shushu Wei, Ying Ju, Fule Li, Zhihua Wang
An 11-bit 200MS/s subrange SAR ADC with charge-compensation-based reference buffer. NEWCAS (2016)
Xuqiang Zheng, Zhijun Wang, Fule Li, Feng Zhao, Shigang Yue, Chun Zhang, Zhihua Wang
A 14-bit 250 MS/s IF Sampling Pipelined ADC in 180 nm CMOS Process. IEEE Trans. Circuits Syst. I Regul. Pap. (9) (2016)
Ying Ju, Fule Li, XiuJu He, Chun Zhang, Zhihua Wang
Aperture error reduction technique for subrange SAR ADC. NEWCAS (2016)
Weitao Li, Fule Li, Ya Wang, Shengjing Li, Chun Zhang, Zhihua Wang
A power-efficient 14-bit 250MS/s pipelined ADC. NEWCAS (2015)
Zhaoyang Weng, Shaoquan Gao, Jingjing Dong, Kai Yang, Hanjun Jiang, Fule Li, Zhihua Wang, Yanqing Ning, Xinkai Chen
Dedicated ICs for wearable body sound monitoring. A-SSCC (2015)
Shengjing Li, Weitao Li, Fule Li, Zhihua Wang, Chun Zhang
A digital blind background calibration algorithm for pipelined ADC. NEWCAS (2015)
Weidong Cao, Ziqiang Wang, Dongmei Li, Xuqiang Zheng, Fule Li, Chun Zhang, Zhihua Wang
A 40Gb/s 39mW 3-tap adaptive closed-loop decision feedback equalizer in 65nm CMOS. MWSCAS (2015)
Qi Peng, Chun Zhang, Xijin Zhao, Xuguang Sun, Fule Li, Hong Chen, Zhihua Wang
A Low-Cost UHF RFID System With OCA Tag for Short-Range Communication. IEEE Trans. Ind. Electron. 62 (7) (2015)
Ke Huang, Deng Luo, Ziqiang Wang, Xuqiang Zheng, Fule Li, Chun Zhang, Zhihua Wang
A 190mW 40Gbps SerDes transmitter and receiver chipset in 65nm CMOS technology. CICC (2015)
Jifang Wu, Fule Li, Weitao Li, Chun Zhang, Zhihua Wang
A 14-bit 200MS/s low-power pipelined flash-SAR ADC. MWSCAS (2015)
Weidong Cao, Ziqiang Wang, Dongmei Li, Xuqiang Zheng, Ke Huang, Shuai Yuan, Fule Li, Zhihua Wang
A 40Gb/s 27mW 3-tap closed-loop decision feedback equalizer in 65nm CMOS. NEWCAS (2015)
Xian Gu, XiuJu He, Fule Li
A calibration technique for SAR ADC based on code density test. ASICON (2015)
Weitao Li, Fule Li, Changyi Yang, Minzeng Li, Zhihua Wang
A power-efficient reference buffer with wide swing for switched-capacitor ADC. Microelectron. J. 46 (5) (2015)
Ya Wang, Fule Li, Chunying Xue, Zhihua Wang
Charge-compensation-based reference technique for switched-capacitor ADCs. ISCAS (2015)
Meng Ni, Fule Li, Weitao Li, Chun Zhang, Zhihua Wang
A high-speed analog front-end circuit used in a 12bit 1GSps pipeline ADC. ASICON (2015)
Fangxu Lv, Xuqiang Zheng, Ziqiang Wang, Jianye Wang, Fule Li
A 50Gb/s low power PAM4 SerDes transmitter with 4-tap FFE and high linearity output voltage in 65nm CMOS technology. ASICON (2015)
Jingjing Dong, Hanjun Jiang, Lingwei Zhang, Jianjun Wei, Fule Li, Chun Zhang, Zhihua Wang
A low-power DC offset calibration method independent of IF gain for zero-IF receiver. Sci. China Inf. Sci. 57 (10) (2014)
Weitao Li, Cao Sun, Fule Li, Zhihua Wang
A 14-bit pipelined ADC with digital background nonlinearity calibration. ISCAS (2013)
Lingwei Zhang, Hanjun Jiang, Fule Li, Jingjing Dong, Zhihua Wang
A LUT-free DC offset calibration method for removing the PGA-gain-correlated offset residue. ISCAS (2013)
Lingwei Zhang, Hanjun Jiang, Jianjun Wei, Jingjing Dong, Fule Li, Weitao Li, Jia Gao, Jianwei Cui, Baoyong Chi, Chun Zhang, Zhihua Wang
A Reconfigurable Sliding-IF Transceiver for 400 MHz/2.4 GHz IEEE 802.15.6/ZigBee WBAN Hubs With Only 21% Tuning Range VCO. IEEE J. Solid State Circuits 48 (11) (2013)
Zhihua Wang, Hanjun Jiang, Kai Yang, Lingwei Zhang, Jianjun Wei, Fule Li, Baoyong Chi, Chun Zhang, Shouhao Wu, Qingliang Lin, Wen Jia
Lifetime tracing of cardiopulmonary sounds with ultra-low-power sound sensor stick connected to wireless mobile network. NEWCAS (2013)
Changyi Yang, Weitao Li, Fule Li, Zhihua Wang
A merged first and second stage for low power pipelined ADC. ISCAS (2013)
Chenchen Zhao, Lili Xu, Fule Li, Zhihua Wang
An efficient calibration technique for pipeline ADC. MWSCAS (2013)
Xuqiang Zheng, Fule Li, Xuan Wang, Chun Zhang
A current-to-voltage integrator using area-efficient correlated double sampling technique. ISCAS (2012)
Xuan Wang, Changyi Yang, Xiaoxiao Zhao, Chao Wu, Fule Li, Zhihua Wang, Bin Wu
A 12-bit, 270MS/s pipelined ADC with SHA-eliminating front end. ISCAS (2012)
Xiaoyu Zhang, Hanjun Jiang, Fule Li, Songyuan Cheng, Chun Zhang, Zhihua Wang
An energy-efficient SoC for closed-loop medical monitoring and intervention. CICC (2010)
Qiuling Zhu, Chun Zhang, Zhongqi Liu, Jingchao Wang, Fule Li, Zhihua Wang
A Robust Radio Frequency Identification System Enhanced with Spread Spectrum Technique. ISCAS (2009)
Shuaiqi Wang, Fule Li, Yasuaki Inoue
A 12-bit 3.7-Msample/s Pipelined A/D Converter Based on the Novel Capacitor Mismatch Calibration Technique. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (9) (2008)
Jingbo Duan, Fule Li, Liyuan Liu, Dongmei Li, Yongming Li, Zhihua Wang
A Pipelined A/D Conversion Technique with Low INL and DNL. ISCAS (2007)
Fule Li, Zhihua Wang, Dongmei Li
An Incomplete Settling Technique for Pipelined Analog-to-Digital Converters. ISCAS (2007)
Shuaiqi Wang, Fule Li, Yasuaki Inoue
A 15-bit 10-Msample/s Pipelined A/D Converter Based on Incomplete Settling Principle. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (10) (2006)