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A 14-bit 200-Ms/s SHA-Less Pipelined ADC With Aperture Error Reduction.
Peilin Yang
Xiao Wang
Chengwei Wang
Fule Li
Hanjun Jiang
Zhihua Wang
Published in:
IEEE Trans. Very Large Scale Integr. Syst. (2020)
Keyphrases
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error reduction
analog to digital converter
classification error
semi supervised
classification accuracy
iterative learning
imaging systems
significant improvement
hash functions
instruction set architecture
feature selection
high resolution
class labels
training samples
learning process
training set
data sets