Xiao Wang

Publication Activity (10 Years)

Years Active: 2016-2022
Publications (10 Years): 10

Top Topics

Synthetic Aperture Radar

Instruction Set Architecture

Wide Dynamic Range

Analog To Digital Converter

Top Venues

IEEE Trans. Very Large Scale Integr. Syst.

IEEE Trans. Circuits Syst. I Regul. Pap.

Publications

Meng Ni, Xiao Wang, Fule Li, Woogeun Rhee, Zhihua Wang
A 13-Bit 2-GS/s Time-Interleaved ADC With Improved Correlation-Based Timing Skew Calibration Strategy. IEEE Trans. Circuits Syst. I Regul. Pap. 69 (2) (2022)
Meng Ni, Xiao Wang, Fule Li, Zhihua Wang
A 13-bit 312.5-MS/s Pipelined SAR ADC With Open-Loop Integrator-Based Residue Amplifier and Gain-Stabilized Integration Time Generation. IEEE Trans. Very Large Scale Integr. Syst. 29 (7) (2021)
Xiao Wang, Fule Li, Zhihua Wang
A Simple Histogram-Based Capacitor Mismatch Calibration in SAR ADCs. IEEE Trans. Circuits Syst. (12) (2020)
Meng Ni, Xiao Wang, Zhe Zhou, Yang Ding, Fule Li, Woogeun Rhee, Zhihua Wang
A 13-bit 312.5-MS/s Pipelined SAR ADC with Integrator-type Residue Amplifier and Inter-stage Gain Stabilization Technique. MWSCAS (2020)
Meng Ni, Xiao Wang, Zhe Zhou, Yang Ding, Fule Li, Woogeun Rhee, Zhihua Wang
A Correlation-based Timing Skew Calibration Strategy Using a Time-Interleaved Reference ADC. MWSCAS (2020)
Peilin Yang, Xiao Wang, Chengwei Wang, Fule Li, Hanjun Jiang, Zhihua Wang
A 14-bit 200-Ms/s SHA-Less Pipelined ADC With Aperture Error Reduction. IEEE Trans. Very Large Scale Integr. Syst. 28 (9) (2020)
Xiao Wang, Fule Li, Wen Jia, Zhihua Wang
A 14-Bit 500-MS/s Time-Interleaved ADC With Autocorrelation-Based Time Skew Calibration. IEEE Trans. Circuits Syst. II Express Briefs (2) (2019)
Chengwei Wang, Xiao Wang, Yang Ding, Fule Li, Zhihua Wang
A 14-bit 250MS/s Low-Power Pipeline ADC with Aperture Error Eliminating Technique. ISCAS (2018)
Xiao Wang, Chengwei Wang, Fule Li, Zhihua Wang
A Low-Power 12-bit 2GS/s Time-Interleaved Pipelined-SAR ADC in 28nm CMOS Process. ISCAS (2018)
Xiao Wang, Fule Li, Zhihua Wang
A novel autocorrelation-based timing mismatch C alibration strategy in Time-Interleaved ADCs. ISCAS (2016)