A Low-Power 12-bit 2GS/s Time-Interleaved Pipelined-SAR ADC in 28nm CMOS Process.
Xiao WangChengwei WangFule LiZhihua WangPublished in: ISCAS (2018)
Keyphrases
- low power
- analog to digital converter
- nm technology
- cmos technology
- power consumption
- mixed signal
- high speed
- single chip
- low cost
- image sensor
- vlsi circuits
- power reduction
- high power
- sar images
- wireless transmission
- logic circuits
- low power consumption
- digital signal processing
- image reconstruction
- cmos image sensor
- vlsi architecture
- linear array
- low voltage
- wide dynamic range
- data flow
- image compression
- instruction set architecture