A merged first and second stage for low power pipelined ADC.
Changyi YangWeitao LiFule LiZhihua WangPublished in: ISCAS (2013)
Keyphrases
- low power
- single chip
- power consumption
- low cost
- high speed
- digital signal processing
- high power
- vlsi architecture
- vlsi circuits
- logic circuits
- wireless transmission
- low power consumption
- analog to digital converter
- image sensor
- data flow
- mixed signal
- delay insensitive
- energy dissipation
- power dissipation
- image processing
- gate array
- power reduction
- multi channel
- video sequences