A 12-bit, 270MS/s pipelined ADC with SHA-eliminating front end.

Xuan Wang Changyi Yang Xiaoxiao Zhao Chao Wu Fule Li Zhihua Wang Bin Wu

Published in: ISCAS (2012)

Keyphrases

multiple sclerosis
analog to digital converter
back end
hash functions
bit vector
bit vectors
website
hash table
magnetic tape
real time
neural network
data mining
artificial intelligence
parallel processing
block cipher
instruction set architecture