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A 50Gb/s low power PAM4 SerDes transmitter with 4-tap FFE and high linearity output voltage in 65nm CMOS technology.
Fangxu Lv
Xuqiang Zheng
Ziqiang Wang
Jianye Wang
Fule Li
Published in:
ASICON (2015)
Keyphrases
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cmos technology
low power
high speed
power consumption
low cost
low power consumption
low voltage
single chip
mixed signal
silicon on insulator
real time
power dissipation
power management
image sensor
output voltage
vlsi architecture
hardware and software
frame rate
image processing