Fangxu Lv

Publication Activity (10 Years)

Years Active: 2014-2024
Publications (10 Years): 24

Top Topics

Fpga Implementation

Top Venues

Microelectron. J.

Publications

Yu He, Xuqiang Zhenq, Zedong Wang, Zunsong Yanq, Hua Xu, Fangxu Lv, Mingche Lai, Xinyu Liu
An Injection-Locked Clock Multiplier with Adaptive Pulsewidth Adjustment and Phase Error Cancellation Achieving 43.9fs RMS Jitter and -255.5dB FoM. CICC (2024)
Zhang Luo, Sichun Du, Zedi Zhang, Fangxu Lv, Qinghui Hong, Mingche Lai
Artificial Neural Network Based on Memristive Circuit for High-Speed Equalization. IEEE Trans. Circuits Syst. I Regul. Pap. 71 (4) (2024)
Chaolong Xu, Fangxu Lv, Zhengbin Pang, Liquan Xiao, Zhouhao Yang
FPGA Implementation of Sequence Detector for High-Speed PAM4 Wireline Transceiver. ACM Great Lakes Symposium on VLSI (2024)
Kewei Xin, Mingche Lai, Fangxu Lv, Xuqiang Zheng, Kaile Guo, Zhengbin Pang, Chaolong Xu, Geng Zhang, Wenchen Wang, Meng Li
Frequency Domain Modeling and Performance Analysis of Injection-Locked LC Oscillator. IEEE Trans. Circuits Syst. II Express Briefs 71 (1) (2024)
Qing Liu, Heming Wang, Fangxu Lv, Geng Zhang, Dongbin Lv
Low-Jitter Retimer Circuits for High-Performance Computer Optical Communications. ICCEIC (2023)
Qiuyue Zhang, Xuqiang Zheng, Fangxu Lv, Zhaoyang Liu, Hua Xu, Weijie Li, Zhi Jin, Mingche Lai, Xinyu Liu
A 50 Gb/s PAM-4 EAM driver in 28-nm CMOS technology. Microelectron. J. 140 (2023)
Mingche Lai, Fangxu Lv, Geng Zhang, Chaolong Xu
A Low BER Cooperative-adaptive-equalizer for Serial Receiver in HPC Networks. HPCC/DSS/SmartCity/DependSys (2023)
Mingche Lai, Geng Zhang, Fangxu Lv, Xuqiang Zheng, Heming Wang, Dongbin Lv, Chaolong Xu, Xingyun Qi
A 33.33 Gb/s/wire pin-efficient 1.06 pJ/bit wireline transceiver based on CNRZ-5 for Chiplet in 28 nm CMOS. Microelectron. J. 130 (2022)
Miaomiao Wu, Zhengbin Pang, Fangxu Lv, Jianjun Shi, Heming Wang, Tao Liu, Dechao Lu, Zheng Wang
An Adaptive Equalization Algorithm for High Speed SerDes. ASICON (2021)
Zhang Geng, Fangxu Lv, Zhengbin Pang, Heming Wang, Dongbin Lv, Tao Liu, Jinwang Zhang
A 5-156.25Gb/s high pin efficiency Receiver Based on CNRZ-5 for USR High-Speed Interface. ASICON (2021)
Tao Liu, Fangxu Lv, Bin Liang, Heming Wang, Jianye Wang, Miaomiao Wu
An Analytical Jitter Transfer Model for Mueller-Muller Clock and Data Recovery Circuits. ASICON (2021)
Xuqiang Zheng, Hao Ding, Feng Zhao, DanYu Wu, Lei Zhou, Jin Wu, Fangxu Lv, Jianye Wang, Xinyu Liu
A 50-112-Gb/s PAM-4 Transmitter With a Fractional-Spaced FFE in 65-nm CMOS. IEEE J. Solid State Circuits 55 (7) (2020)
Zhengbin Pang, Fangxu Lv, Weiping Tang, Mingche Lai, Kaile Guo, Yuxuan Wu, Tao Liu, Miaomiao Wu, Dechao Lu
A 32 Gb/s Low Power Little Area Re-timer with PI Based CDR in 65 nm CMOS Technology. ACA (2020)
Xuqiang Zheng, Fangxu Lv, Lei Zhou, DanYu Wu, Jin Wu, Chun Zhang, Woogeun Rhee, Xinyu Liu
Frequency-Domain Modeling and Analysis of Injection-Locked Oscillators. IEEE J. Solid State Circuits 55 (6) (2020)
Dengjie Wang, Hong Chen, Wenhuan Luan, Xin Lin, Fangxu Lv, Ziqiang Wang, Hanjun Jiang, Chun Zhang, Zhihua Wang
A 4-40 Gb/s PAM-4 transmitter with a hybrid driver in 65 nm CMOS technology. MWSCAS (2019)
Hao Ding, Xuqiang Zheng, DanYu Wu, Lei Zhou, Jin Wu, Fangxu Lv, Jianye Wang, Xinyu Liu
A 112-Gb/s PAM-4 Transmitter With a 2-Tap Fractional-Spaced FFE in 65-nm CMOS. ESSCIRC (2019)
Fangxu Lv, Xuqiang Zheng, Feng Zhao, Jianye Wang, Shigang Yue, Ziqiang Wang, Weidong Cao, Yajun He, Chun Zhang, Hanjun Jiang, Zhihua Wang
A power scalable 2-10 Gb/s PI-based clock data recovery for multilane applications. Microelectron. J. 82 (2018)
Xuqiang Zheng, Chun Zhang, Fangxu Lv, Feng Zhao, Shigang Yue, Ziqiang Wang, Fule Li, Hanjun Jiang, Zhihua Wang
A 4-40 Gb/s PAM4 transmitter with output linearity optimization in 65 nm CMOS. CICC (2017)
Yajun He, Ziqiang Wang, Han Liu, Fangxu Lv, Shuai Yuan, Chun Zhang, Zhihua Wang, Hanjun Jiang
An 8.5-12.5GHz wideband LC PLL with dual VCO cores for multi-protocol SerDes. MWSCAS (2017)
Fangxu Lv, Xuqiang Zheng, Shuai Yuan, Ziqiang Wang, Yajun He, Chun Zhang, Zhihua Wang, Jianye Wang
A 40-80 Gb/s PAM4 wireline transmitter in 65nm CMOS technology. MWSCAS (2017)
Fangxu Lv, Jianye Wang, Dengjie Wang, Yongcong Liu, Ziqiang Wang
Design of 56 Gb/s PAM4 wire-line receiver with ring VCO based CDR in a 65 nm CMOS technology. ASICON (2017)
Xuqiang Zheng, Fangxu Lv, Feng Zhao, Shigang Yue, Chun Zhang, Ziqiang Wang, Fule Li, Hanjun Jiang, Zhihua Wang
A 10 GHz 56 fsrms-integrated-jitter and -247 dB FOM ring-VCO based injection-locked clock multiplier with a continuous frequency-tracking loop in 65 nm CMOS. CICC (2017)
Xuqiang Zheng, Chun Zhang, Fangxu Lv, Feng Zhao, Shuai Yuan, Shigang Yue, Ziqiang Wang, Fule Li, Zhihua Wang, Hanjun Jiang
A 40-Gb/s Quarter-Rate SerDes Transmitter and Receiver Chipset in 65-nm CMOS. IEEE J. Solid State Circuits 52 (11) (2017)
Xuqiang Zheng, Chun Zhang, Fangxu Lv, Feng Zhao, Shigang Yue, Ziqiang Wang, Fule Li, Zhihua Wang
A 5-50 Gb/s quarter rate transmitter with a 4-tap multiple-MUX based FFE in 65 nm CMOS. ESSCIRC (2016)
Fangxu Lv, Xuqiang Zheng, Ziqiang Wang, Jianye Wang, Fule Li
A 50Gb/s low power PAM4 SerDes transmitter with 4-tap FFE and high linearity output voltage in 65nm CMOS technology. ASICON (2015)
Yu Wang, Jincheng Zhang, Quan Wang, Fangxu Lv, Kewei Chen
Compressive Spectrum Sensing Based on Sparse Sub-band Basis in Wireless Sensor Network. CWSN (2014)