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Design of 56 Gb/s PAM4 wire-line receiver with ring VCO based CDR in a 65 nm CMOS technology.
Fangxu Lv
Jianye Wang
Dengjie Wang
Yongcong Liu
Ziqiang Wang
Published in:
ASICON (2017)
Keyphrases
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cmos technology
low power
spl times
parallel processing
power consumption
power dissipation
low voltage
low cost
high speed
mixed signal
case study
real time
digital images
design methodology
image processing algorithms
digital signal processing