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FPGA Implementation of Sequence Detector for High-Speed PAM4 Wireline Transceiver.

Chaolong XuFangxu LvZhengbin PangLiquan XiaoZhouhao Yang
Published in: ACM Great Lakes Symposium on VLSI (2024)
Keyphrases
  • fpga implementation
  • high speed
  • hardware implementation
  • low power
  • wireless networks
  • image processing algorithms
  • ds cdma
  • neural network
  • case study
  • image segmentation
  • feature extraction
  • pairwise