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A 32 Gb/s Low Power Little Area Re-timer with PI Based CDR in 65 nm CMOS Technology.
Zhengbin Pang
Fangxu Lv
Weiping Tang
Mingche Lai
Kaile Guo
Yuxuan Wu
Tao Liu
Miaomiao Wu
Dechao Lu
Published in:
ACA (2020)
Keyphrases
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cmos technology
low power
high speed
low cost
power consumption
low voltage
single chip
silicon on insulator
mixed signal
power dissipation
image sensor
digital signal processing
low power consumption
power reduction
real time
frame rate
high resolution
pattern recognition