Xuqiang Zheng

ORCID

Publication Activity (10 Years)

Years Active: 2012-2024
Publications (10 Years): 31

Top Venues

CICC

ESSCIRC

IEEE Trans. Circuits Syst. I Regul. Pap.

IEEE J. Solid State Circuits

University of Lincoln, UK (PHD)

Education History

University of Lincoln, UK

PHD

Publications

Kewei Xin, Mingche Lai, Fangxu Lv, Xuqiang Zheng, Kaile Guo, Zhengbin Pang, Chaolong Xu, Geng Zhang, Wenchen Wang, Meng Li
Frequency Domain Modeling and Performance Analysis of Injection-Locked LC Oscillator. IEEE Trans. Circuits Syst. II Express Briefs 71 (1) (2024)
Qiuyue Zhang, Xuqiang Zheng, Fangxu Lv, Zhaoyang Liu, Hua Xu, Weijie Li, Zhi Jin, Mingche Lai, Xinyu Liu
A 50 Gb/s PAM-4 EAM driver in 28-nm CMOS technology. Microelectron. J. 140 (2023)
Geng Zhang, Mingche Lai, Fangxu Lyu, Xuqiang Zheng, Heming Wang, Dongbin Lv, Chaolong Xu, Xingyun Qi, Qing Liu
A CNRZ-7 Based Wireline Transceiver With High-Bandwidth-Density, Low-Power for D2D Communication. IEEE Access 10 (2022)
Mingche Lai, Geng Zhang, Fangxu Lv, Xuqiang Zheng, Heming Wang, Dongbin Lv, Chaolong Xu, Xingyun Qi
A 33.33 Gb/s/wire pin-efficient 1.06 pJ/bit wireline transceiver based on CNRZ-5 for Chiplet in 28 nm CMOS. Microelectron. J. 130 (2022)
Jian Luan, Danyu Wu, Xuqiang Zheng, Chen Cai, Linzhen Wu, Lei Zhou, Jin Wu, Xinyu Liu
A Real-Time Output 50-GS/s 8-bit TI-ADC with Dedicated Calibration Techniques and Deterministic Latency. ESSCIRC (2021)
Chen Cai, Xuqiang Zheng, Yong Chen, Danyu Wu, Jian Luan, Lei Zhou, Jin Wu, Xinyu Liu
A 1.4-Vppd 64-Gb/s PAM-4 Transmitter with 4-Tap Hybrid FFE Employing Fractionally-Spaced Pre-Emphasis and Baud-Spaced De-Emphasis in 28-nm CMOS. ESSCIRC (2021)
Xuqiang Zheng, Hao Ding, Feng Zhao, DanYu Wu, Lei Zhou, Jin Wu, Fangxu Lv, Jianye Wang, Xinyu Liu
A 50-112-Gb/s PAM-4 Transmitter With a Fractional-Spaced FFE in 65-nm CMOS. IEEE J. Solid State Circuits 55 (7) (2020)
Xuqiang Zheng, Chun Zhang, Ping Chen, Kang Zhao, Hanjun Jiang, Zhiwei Jiang, Huafeng Pan, Zhihua Wang, Wen Jia
A CRNN System for Sound Event Detection Based on Gastrointestinal Sound Dataset Collected by Wearable Auscultation Devices. IEEE Access 8 (2020)
Hongxin Wang, Jigen Peng, Xuqiang Zheng, Shigang Yue
A Robust Visual System for Small Target Motion Detection Against Cluttered Moving Backgrounds. IEEE Trans. Neural Networks Learn. Syst. 31 (3) (2020)
Xuqiang Zheng, Fangxu Lv, Lei Zhou, DanYu Wu, Jin Wu, Chun Zhang, Woogeun Rhee, Xinyu Liu
Frequency-Domain Modeling and Analysis of Injection-Locked Oscillators. IEEE J. Solid State Circuits 55 (6) (2020)
Huasen Liu, DanYu Wu, Lei Zhou, Yinkun Huang, Jian Luan, Xuan Guo, Dong Wang, Xuqiang Zheng, Jin Wu, Xinyu Liu
A 10-GS/s 8-bit 4-way interleaved folding ADC in 0.18 µm SiGe-BiCMOS. IEICE Electron. Express 16 (3) (2019)
Hongxin Wang, Jigen Peng, Xuqiang Zheng, Shigang Yue
A Robust Visual System for Small Target Motion Detection Against Cluttered Moving Backgrounds. CoRR (2019)
Hao Ding, Xuqiang Zheng, DanYu Wu, Lei Zhou, Jin Wu, Fangxu Lv, Jianye Wang, Xinyu Liu
A 112-Gb/s PAM-4 Transmitter With a 2-Tap Fractional-Spaced FFE in 65-nm CMOS. ESSCIRC (2019)
Fangxu Lv, Xuqiang Zheng, Feng Zhao, Jianye Wang, Shigang Yue, Ziqiang Wang, Weidong Cao, Yajun He, Chun Zhang, Hanjun Jiang, Zhihua Wang
A power scalable 2-10 Gb/s PI-based clock data recovery for multilane applications. Microelectron. J. 82 (2018)
Xuqiang Zheng, Chun Zhang, Fangxu Lv, Feng Zhao, Shigang Yue, Ziqiang Wang, Fule Li, Hanjun Jiang, Zhihua Wang
A 4-40 Gb/s PAM4 transmitter with output linearity optimization in 65 nm CMOS. CICC (2017)
Fangxu Lv, Xuqiang Zheng, Shuai Yuan, Ziqiang Wang, Yajun He, Chun Zhang, Zhihua Wang, Jianye Wang
A 40-80 Gb/s PAM4 wireline transmitter in 65nm CMOS technology. MWSCAS (2017)
Shiquan Fan, Liuming Zhao, Peng Wang, Ran Wei, Xuqiang Zheng, Zenghui Wang, Philip X.-L. Feng
A battery-less, 255 nA quiescent current temperature sensor with voltage regulator fully powered by harvesting ambient vibrational energy. ISCAS (2017)
Xuqiang Zheng, Fangxu Lv, Feng Zhao, Shigang Yue, Chun Zhang, Ziqiang Wang, Fule Li, Hanjun Jiang, Zhihua Wang
A 10 GHz 56 fsrms-integrated-jitter and -247 dB FOM ring-VCO based injection-locked clock multiplier with a continuous frequency-tracking loop in 65 nm CMOS. CICC (2017)
Xuqiang Zheng, Chun Zhang, Fangxu Lv, Feng Zhao, Shuai Yuan, Shigang Yue, Ziqiang Wang, Fule Li, Zhihua Wang, Hanjun Jiang
A 40-Gb/s Quarter-Rate SerDes Transmitter and Receiver Chipset in 65-nm CMOS. IEEE J. Solid State Circuits 52 (11) (2017)
Xuqiang Zheng, Chun Zhang, Fangxu Lv, Feng Zhao, Shigang Yue, Ziqiang Wang, Fule Li, Zhihua Wang
A 5-50 Gb/s quarter rate transmitter with a 4-tap multiple-MUX based FFE in 65 nm CMOS. ESSCIRC (2016)
Shuai Yuan, Liji Wu, Ziqiang Wang, Xuqiang Zheng, Chun Zhang, Zhihua Wang
A 70 mW 25 Gb/s Quarter-Rate SerDes Transmitter and Receiver Chipset With 40 dB of Equalization in 65 nm CMOS Technology. IEEE Trans. Circuits Syst. I Regul. Pap. (7) (2016)
Xuqiang Zheng, Chun Zhang, Shuai Yuan, Feng Zhao, Shigang Yue, Ziqiang Wang, Fule Li, Zhihua Wang
An improved 40 Gb/s CDR with jitter-suppression filters and phase-compensating interpolators. A-SSCC (2016)
Naiwen Zhou, Linghan Wu, Ziqiang Wang, Xuqiang Zheng, Weidong Cao, Chun Zhang, Fule Li, Zhihua Wang
A 28-Gb/s transmitter with 3-tap FFE and T-coil enhanced terminal in 65-nm CMOS technology. NEWCAS (2016)
Xuqiang Zheng, Zhijun Wang, Fule Li, Feng Zhao, Shigang Yue, Chun Zhang, Zhihua Wang
A 14-bit 250 MS/s IF Sampling Pipelined ADC in 180 nm CMOS Process. IEEE Trans. Circuits Syst. I Regul. Pap. (9) (2016)
Shuai Yuan, Liji Wu, Ziqiang Wang, Xuqiang Zheng, Peng Wang, Wen Jia, Chun Zhang, Zhihua Wang
A 48mW 15-to-28Gb/s source-synchronous receiver with adaptive DFE using hybrid alternate clock scheme and baud-rate CDR in 65nm CMOS. ESSCIRC (2015)
Weidong Cao, Ziqiang Wang, Dongmei Li, Xuqiang Zheng, Fule Li, Chun Zhang, Zhihua Wang
A 40Gb/s 39mW 3-tap adaptive closed-loop decision feedback equalizer in 65nm CMOS. MWSCAS (2015)
Ke Huang, Deng Luo, Ziqiang Wang, Xuqiang Zheng, Fule Li, Chun Zhang, Zhihua Wang
A 190mW 40Gbps SerDes transmitter and receiver chipset in 65nm CMOS technology. CICC (2015)
Ke Huang, Ziqiang Wang, Xuqiang Zheng, Chun Zhang, Zhihua Wang
A 80 mW 40 Gb/s Transmitter With Automatic Serializing Time Window Search and 2-tap Pre-Emphasis in 65 nm CMOS Technology. IEEE Trans. Circuits Syst. I Regul. Pap. (5) (2015)
Shuai Yuan, Liji Wu, Ziqiang Wang, Xuqiang Zheng, Wen Jia, Chun Zhang, Zhihua Wang
A 4×20-Gb/s 0.86pJ/b/lane 2-tap-FFE source-series-terminated transmitter with far-end crosstalk cancellation and divider-less clock generation in 65nm CMOS. CICC (2015)
Weidong Cao, Ziqiang Wang, Dongmei Li, Xuqiang Zheng, Ke Huang, Shuai Yuan, Fule Li, Zhihua Wang
A 40Gb/s 27mW 3-tap closed-loop decision feedback equalizer in 65nm CMOS. NEWCAS (2015)
Fangxu Lv, Xuqiang Zheng, Ziqiang Wang, Jianye Wang, Fule Li
A 50Gb/s low power PAM4 SerDes transmitter with 4-tap FFE and high linearity output voltage in 65nm CMOS technology. ASICON (2015)
Ke Huang, Ziqiang Wang, Xuqiang Zheng, Chun Zhang, Zhihua Wang
A 75mW 50Gbps SerDes transmitter with automatic serializing time window search in 65nm CMOS technology. CICC (2014)
Shuai Yuan, Ziqiang Wang, Xuqiang Zheng, Ke Huang, Ni Xu, Woogeun Rhee, Liji Wu, Chun Zhang
A 4.8-mW/Gb/s 9.6-Gb/s 5 + 1-Lane Source-Synchronous Transmitter in 65-nm Bulk CMOS. IEEE Trans. Circuits Syst. II Express Briefs (4) (2014)
Kunzhi Yu, Xuqiang Zheng, Ke Huang, Xuan Ma, Ziqiang Wang, Chun Zhang, Zhihua Wang
A 6.4 Gb/s source synchronous receiver core with variable offset equalizer in 65nm CMOS. VLSI-DAT (2013)
Linghan Wu, Ziqiang Wang, Ke Huang, Shuai Yuan, Xuqiang Zheng, Chun Zhang, Zhihua Wang
A 10Gb/s analog equalizer in 0.18um CMOS. ASICON (2013)
Shuai Yuan, Ziqiang Wang, Xuqiang Zheng, Ke Huang, Liji Wu, Zhihua Wang
A 10-Gb/s simplified transceiver with a quarter-rate 4-tap decision feedback equalizer in 0.18-μm CMOS technology. ASICON (2013)
Shijie Hu, Chen Jia, Ke Huang, Chun Zhang, Xuqiang Zheng, Zhihua Wang
A 10Gbps CDR based on phase interpolator for source synchronous receiver in 65nm CMOS. ISCAS (2012)
Ke Huang, Ziqiang Wang, Xuqiang Zheng, Xuan Ma, Kunzhi Yu, Chun Zhang, Zhihua Wang
A novel clock and data recovery scheme for 10Gbps source synchronous receiver in 65nm CMOS. MWSCAS (2012)
Xuqiang Zheng, Fule Li, Xuan Wang, Chun Zhang
A current-to-voltage integrator using area-efficient correlated double sampling technique. ISCAS (2012)
Ke Huang, Chen Jia, Xuqiang Zheng, Ni Xu, Chun Zhang, Woogeun Rhee, Zhihua Wang
A 9.6Gb/s 5+1-lane source synchronous transmitter in 65nm CMOS technology. ISCAS (2012)
Kunzhi Yu, Ziqiang Wang, Xuan Ma, Xuqiang Zheng, Chun Zhang, Zhihua Wang
A 6.4 Gb/s data lane design for forwarded clock receiver in 65nm CMOS. MWSCAS (2012)

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Publication Activity (10 Years)

Top Topics

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Xuqiang Zheng