A 6.4 Gb/s data lane design for forwarded clock receiver in 65nm CMOS.
Kunzhi YuZiqiang WangXuan MaXuqiang ZhengChun ZhangZhihua WangPublished in: MWSCAS (2012)
Keyphrases
- data sets
- image data
- data analysis
- case study
- data sources
- high speed
- raw data
- training data
- high quality
- synthetic data
- data collection
- data processing
- probability distribution
- original data
- data quality
- knowledge discovery
- prior knowledge
- databases
- data integrity
- circuit design
- database
- computer systems
- data mining techniques
- real time