Kunzhi Yu

Publication Activity (10 Years)

Years Active: 2012-2023
Publications (10 Years): 6

Top Topics

Computer Science Students

Energy Efficiency

Top Venues

IEEE J. Solid State Circuits

Publications

Harsh Kumar, Kunzhi Yu, Andrew Chung, Jiakai Shi, Joseph Jay Williams
Exploring The Potential of Chatbots to Provide Mental Well-being Support for Computer Science Students. SIGCSE (2) (2023)
Di Liang, Chong Zhang, Ashkan Roshan-Zamir, Kunzhi Yu, Cheng Li, Geza Kurczveil, Yingtao Hu, Wenqing Shen, Marco Fiorentino, Satish Kumar, Samuel Palermo, Raymond G. Beausoleil
A Fully-integrated Multi-λ Hybrid DML Transmitter. OFC (2018)
Cheng Li, Kunzhi Yu, Jinsoo Rhim, Kehan Zhu, Nan Qi, Marco Fiorentino, Thierry Pinguet, Mark Peterson, Vishal Saxena, Samuel Palermo
A 3D-Integrated 56 Gb/s NRZ/PAM4 Reconfigurable Segmented Mach-Zehnder Modulator-Based Si-Photonics Transmitter. BCICTS (2018)
Ashkan Roshan-Zamir, Kunzhi Yu, Di Liang, Chong Zhang, Cheng Li, Gaofeng Fan, Binhao Wang, Marco Fiorentino, Raymond G. Beausoleil, Samuel Palermo
A 14 Gb/s Directly Modulated Hybrid Microring Laser Transmitter. OFC (2018)
Ashkan Roshan-Zamir, Binhao Wang, Kunzhi Yu, Shashank Telaprolu, Cheng Li, M. Ashkan Seyedi, Marco Fiorentino, Raymond G. Beausoleil, Samuel Palermo
A 40Gb/s PAM4 optical DAC silicon microring resonator modulator transmitter. MWSCAS (2017)
Kunzhi Yu, Cheng Li, Hao Li, Alex Titriku, Ayman Shafik, Binhao Wang, Zhongkai Wang, Rui Bai, Chin-Hui Chen, Marco Fiorentino, Patrick Yin Chiang, Samuel Palermo
A 25 Gb/s Hybrid-Integrated Silicon Photonic Source-Synchronous Receiver With Microring Wavelength Stabilization. IEEE J. Solid State Circuits 51 (9) (2016)
Kunzhi Yu, Hao Li, Cheng Li, Alex Titriku, Ayman Shafik, Binhao Wang, Zhongkai Wang, Rui Bai, Chin-Hui Chen, Marco Fiorentino, Patrick Yin Chiang, Samuel Palermo
22.4 A 24Gb/s 0.71pJ/b Si-photonic source-synchronous receiver with adaptive equalization and microring wavelength stabilization. ISSCC (2015)
Hao Li, Zhe Xuan, Alex Titriku, Cheng Li, Kunzhi Yu, Binhao Wang, Ayman Shafik, Nan Qi, Yang Liu, Ran Ding, Tom Baehr Jones, Marco Fiorentino, Michael Hochberg, Samuel Palermo, Patrick Yin Chiang
22.6 A 25Gb/s 4.4V-swing AC-coupled Si-photonic microring transmitter with 2-tap asymmetric FFE and dynamic thermal tuning in 65nm CMOS. ISSCC (2015)
Kunzhi Yu, Chin-Hui Chen, Cheng Li, Hao Li, Alex Titriku, Binhao Wang, Ayman Shafik, Zhongkai Wang, Marco Fiorentino, Patrick Yin Chiang, Samuel Palermo
25Gb/s hybrid-integrated silicon photonic receiver with microring wavelength stabilization. OFC (2015)
Hao Li, Zhe Xuan, Alex Titriku, Cheng Li, Kunzhi Yu, Binhao Wang, Ayman Shafik, Nan Qi, Yang Liu, Ran Ding, Tom Baehr Jones, Marco Fiorentino, Michael Hochberg, Samuel Palermo, Patrick Yin Chiang
A 25 Gb/s, 4.4 V-Swing, AC-Coupled Ring Modulator-Based WDM Transmitter with Wavelength Stabilization in 65 nm CMOS. IEEE J. Solid State Circuits 50 (12) (2015)
Binhao Wang, Kunzhi Yu, Hao Li, Patrick Yin Chiang, Samuel Palermo
Energy efficiency comparisons of NRZ and PAM4 modulation for ring-resonator-based silicon photonic links. MWSCAS (2015)
Kunzhi Yu, Cheng Li, Tsung-Ching Huang, M. Ashkan Seyedi, Dacheng Zhou, Christopher Wilson, Daniel A. Berkram, Samuel Palermo, Jonathan Q. Smela, Marco Fiorentino, Raymond G. Beausoleil
56 Gb/s PAM-4 optical receiver frontend in an advanced FinFET process. MWSCAS (2015)
M. Ashkan Seyedi, Kunzhi Yu, Cheng Li, Tsung-Ching Huang, Dan Berkram, Christopher Wilson, Ranojoy Bose, Marco Fiorentino, Raymond G. Beausoleil
Silicon Mach-Zehnder Interferometer modulator with PAM-4 data modulation at 64 Gb/s. MWSCAS (2015)
Kunzhi Yu, Xuqiang Zheng, Ke Huang, Xuan Ma, Ziqiang Wang, Chun Zhang, Zhihua Wang
A 6.4 Gb/s source synchronous receiver core with variable offset equalizer in 65nm CMOS. VLSI-DAT (2013)
Ke Huang, Ziqiang Wang, Xuqiang Zheng, Xuan Ma, Kunzhi Yu, Chun Zhang, Zhihua Wang
A novel clock and data recovery scheme for 10Gbps source synchronous receiver in 65nm CMOS. MWSCAS (2012)
Kunzhi Yu, Ziqiang Wang, Xuan Ma, Xuqiang Zheng, Chun Zhang, Zhihua Wang
A 6.4 Gb/s data lane design for forwarded clock receiver in 65nm CMOS. MWSCAS (2012)