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A 6.4 Gb/s source synchronous receiver core with variable offset equalizer in 65nm CMOS.
Kunzhi Yu
Xuqiang Zheng
Ke Huang
Xuan Ma
Ziqiang Wang
Chun Zhang
Zhihua Wang
Published in:
VLSI-DAT (2013)
Keyphrases
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high speed
decision feedback
computer simulation
nm technology
cmos technology
power consumption
low power
low cost
silicon on insulator
metal oxide semiconductor
wireless networks
multiple sources
multipath
power supply
error propagation