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A 48mW 15-to-28Gb/s source-synchronous receiver with adaptive DFE using hybrid alternate clock scheme and baud-rate CDR in 65nm CMOS.

Shuai YuanLiji WuZiqiang WangXuqiang ZhengPeng WangWen JiaChun ZhangZhihua Wang
Published in: ESSCIRC (2015)
Keyphrases
  • power consumption
  • high speed
  • low power
  • nm technology
  • power supply
  • cmos technology
  • decision feedback
  • low cost
  • hd video
  • silicon on insulator
  • allocation scheme
  • channel capacity