A 190mW 40Gbps SerDes transmitter and receiver chipset in 65nm CMOS technology.
Ke HuangDeng LuoZiqiang WangXuqiang ZhengFule LiChun ZhangZhihua WangPublished in: CICC (2015)
Keyphrases
- cmos technology
- power consumption
- low power
- power supply
- received signal
- multiple input multiple output
- spl times
- power dissipation
- channel state information
- low voltage
- power management
- parallel processing
- silicon on insulator
- fading channels
- low cost
- signal to noise ratio
- digital signal processing
- mixed signal
- image sensor
- spatially varying
- image formation
- image restoration