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A 12-Bit 2-GS/s Pipelined ADC Front-End Stage with Aperture Error Tuning and Split MDAC.
Peilin Yang
Fule Li
Zhihua Wang
Published in:
ISCAS (2021)
Keyphrases
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error rate
back end
error bounds
parameter tuning
analog to digital converter
database
high resolution
collaborative learning
multi view
estimation error
data flow
learning stage
random access memory
magnetic tape