Stephan Niel

Publication Activity (10 Years)

Years Active: 2014-2023
Publications (10 Years): 10

Top Topics

Cmos Technology

Top Venues

Publications

Radouane Habhab, Vincenzo Della Marca, Pascal Masson, Nadia Miridi, Clement Pribat, Simon Jeannot, Thibault Kempf, Marc Mantelli, Philippe Lorenzini, Jean-Marc Voisin, Arnaud Régnier, Stephan Niel, Francesco La Rosa
40nm SONOS Embedded Select in Trench Memory. ESSDERC (2023)
Paul Devoge, Hassen Aziza, Philippe Lorenzini, Alexandre Malherbe, Franck Julien, Abderrezak Marzaki, Arnaud Régnier, Stephan Niel
Digital-to-analog converters to benchmark the matching performance of a new zero-cost transistor. ISCAS (2022)
Paul Devoge, Hassen Aziza, Philippe Lorenzini, Pascal Masson, Alexandre Malherbe, Franck Julien, Abderrezak Marzaki, Arnaud Régnier, Stephan Niel
A Schmitt trigger to benchmark the performance of a new zero-cost transistor. ICECS 2022 (2022)
Paul Devoge, Hassen Aziza, Philippe Lorenzini, Franck Julien, Abderrezak Marzaki, Alexandre Malherbe, Marc Mantelli, Thomas Sardin, Sébastien Haendler, Arnaud Régnier, Stephan Niel
Circuit-level evaluation of a new zero-cost transistor in an embedded non-volatile memory CMOS technology. DTIS (2021)
Franck Melul, Thibault Kempf, Vincenzo Della Marca, Marc Bocquet, Madjid Akbal, Frederique Trenteseaux, Marc Mantelli, Arnaud Régnier, Stephan Niel, Francesco La Rosa
Hot Electron Source Side Injection Comprehension in 40nm eSTM™. IMW (2021)
Romeric Gay, Vincenzo Della Marca, Hassen Aziza, Arnaud Régnier, Stephan Niel, Abderrezak Marzaki
Benchmarking and optimization of trench-based multi-gate transistors in a 40 nm non-volatile memory technology. DTIS (2021)
Jordan Locati, Vincenzo Della Marca, Christian Rivero, Arnaud Régnier, Stephan Niel, Karine Coulié
AC stress reliability study of a new high voltage transistor for logic memory circuits. IRPS (2020)
T. Kempf, Vincenzo Della Marca, L. Baron, F. Maugain, F. La Rosa, Stephan Niel, Arnaud Régnier, Jean-Michel Portal, Pascal Masson
Threshold voltage bitmap analysis methodology: Application to a 512kB 40nm Flash memory test chip. IRPS (2018)
Jordan Innocenti, Franck Julien, Jean-Michel Portal, Laurent Lopez, Q. Hubert, Pascal Masson, Jacques Sonzogni, Stephan Niel, Arnaud Régnier
Layout optimizations to decrease internal power and area in digital CMOS standard cells. MIPRO (2015)
Jordan Innocenti, Loïc Welter, Nicolas Borrel, Franck Julien, Jean-Michel Portal, Jacques Sonzogni, Laurent Lopez, Pascal Masson, Stephan Niel, Philippe Dreux, Julia Castellan
Dynamic current reduction of CMOS digital circuits through design and process optimization. PATMOS (2015)
Jordan Innocenti, Loic Welter, Franck Julien, Laurent Lopez, Jacques Sonzogni, Stephan Niel, Arnaud Régnier, Emmanuel Paire, Karen Labory, Eric Denis, Jean-Michel Portal, Pascal Masson
Dynamic power reduction through process and design optimizations on CMOS 80 nm embedded non-volatile memories technology. MWSCAS (2014)